EP2SGX90EF1152I4N Altera, EP2SGX90EF1152I4N Datasheet - Page 150

• Manufacturer Part Number: EP2SGX90EF1152I4N
• Description: Stratix II GX
• Manufacturer: Altera

Specifications of EP2SGX90EF1152I4N

• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / Rohs Status: Compliant

Referenced Documents
Figure 2–91. Fast PLL and Channel Layout in the EP2SGX60E to EP2SGX130 Devices
Note to
(1)
Referenced
Documents
2–142
Stratix II GX Device Handbook, Volume 1
See
Figure
Tables 2–39
2–91:
2
4
2
through
2
2
Tables 2–41
4
4
This chapter references the following documents:
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■
■
■
■
■
■
■
PLL 7
PLL 1
PLL 2
PLL 8
Fast
Fast
Fast
Fast
DC & Switching Characteristics
Handbook
DSP Blocks in Stratix II GX Devices
Stratix II GX Device Handbook
External Memory Interfaces in Stratix II & Stratix II GX Devices
in volume 2 of the Stratix II GX Device Handbook
High-Speed Differential I/O Interfaces with DPA in Stratix II & Stratix II
GX Devices
PLLs in Stratix II & Stratix II GX Devices
Stratix II GX Device Handbook
Selectable I/O Standards in Stratix II & Stratix II GX Devices
volume 2 of the Stratix II GX Handbook
Stratix II GX Device
Stratix II GX Transceiver Architecture Overview
the Stratix II GX Handbook
LVDS
LVDS
Clock
Clock
for the number of channels each device supports.
chapter in volume 2 of the Stratix II GX Handbook
Clock
Clock
DPA
DPA
Handbook, volume 2
Quadrant
Quadrant
chapter in volume 1 of the Stratix II GX
chapter in Volume 2 of the
chapter in volume 2 of the
Quadrant
Quadrant
chapter in volume 2 of
Altera Corporation
Note (1)
October 2007
chapter in
chapter