EP2SGX90EF1152I4N Altera, EP2SGX90EF1152I4N Datasheet - Page 93

• Manufacturer Part Number: EP2SGX90EF1152I4N
• Description: Stratix II GX
• Manufacturer: Altera

Specifications of EP2SGX90EF1152I4N

• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / Rohs Status: Compliant

Altera Corporation
October 2007
Multiplier
Multiply-accumulator
Two-multipliers adder
Four-multipliers adder
Table 2–22. Multiplier Size and Configurations per DSP Block
DSP Block Mode
Modes of Operation
The adder, subtractor, and accumulate functions of a DSP block have four
modes of operation:
■
■
■
■
Table 2–22
DSP block mode according to size. These modes allow the DSP blocks to
implement numerous applications for DSP including FFTs, complex FIR,
FIR, 2D FIR filters, equalizers, IIR, correlators, matrix multiplication, and
many other functions. The DSP blocks also support mixed modes and
mixed multiplier sizes in the same block. For example, half of one DSP
block can implement one 18 × 18-bit multiplier in multiply-accumulator
mode, while the other half of the DSP block implements four 9 × 9-bit
multipliers in simple multiplier mode.
DSP Block Interface
The Stratix II GX device DSP block input registers can generate a shift
register that can cascade down in the same DSP block column. Dedicated
connections between DSP blocks provide fast connections between the
shift register inputs to cascade the shift register chains. You can cascade
registers within multiple DSP blocks for 9 × 9- or 18 × 18-bit FIR filters
larger than four taps, with additional adder stages implemented in
ALMs. If the DSP block is configured as 36 × 36 bits, the adder, subtractor,
or accumulator stages are implemented in ALMs. Each DSP block can
route the shift register chain out of the block to cascade multiple columns
of DSP blocks.
Four two-multiplier adder
Two four-multiplier adder
eight product outputs
Eight multipliers with
(two 9 × 9 complex
Simple multiplier
Multiply-accumulator
Two-multipliers adder
Four-multipliers adder
multiply)
9 × 9
shows the different number of multipliers possible in each
—
One four-multiplier adder
Four multipliers with four
Two two-multiplier adder
(one 18 × 18 complex
Two 52-bit multiply-
accumulate blocks
product outputs
multiply)
18 × 18
Stratix II GX Device Handbook, Volume 1
Stratix II GX Architecture
One multiplier with one
product output
36 × 36
—
—
—
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