EP2SGX90EF1152I4N Altera, EP2SGX90EF1152I4N Datasheet - Page 27
EP2SGX90EF1152I4N
Manufacturer Part Number
EP2SGX90EF1152I4N
Description
Stratix II GX
Manufacturer
Altera
Datasheet
1.EP2SGX90EF1152I4N.pdf
(316 pages)
Specifications of EP2SGX90EF1152I4N
Family Name
Stratix II GX
Number Of Logic Blocks/elements
90960
# I/os (max)
558
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520448
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / Rohs Status
Compliant
Available stocks
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Altera Corporation
October 2007
The CRU has a built-in switchover circuit to select whether the PLL VCO
is aligned by the reference clock or the data. The optional port
rx_freqlocked monitors when the CRU is in locked-to-data mode.
In the automatic mode, the CRU PLL must be within the prescribed PPM
frequency threshold setting of the CRU reference clock for the CRU to
switch from locked-to-reference to locked-to-data mode.
The automatic switchover circuit can be overridden by using the optional
ports rx_locktorefclk and rx_locktodata.
possible combinations of these two signals.
If the rx_locktorefclk and rx_locktodata ports are not used, the
default is auto mode.
Deserializer (Serial-to-Parallel Converter)
The deserializer converts a serial bitstream into 8, 10, 16, or 20 bits of
parallel data. The deserializer receives the LSB first.
the deserializer.
Table 2–6. Receiver Lock Combinations
rx_locktodata
0
0
1
rx_locktorefclk
0
1
x
Stratix II GX Device Handbook, Volume 1
Stratix II GX Architecture
VCO (Lock to Mode)
Table 2–6
Reference clock
Figure 2–17
Auto
Data
shows the
shows
2–19
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