EP3C16F484I7N Altera, EP3C16F484I7N Datasheet - Page 74

• Manufacturer Part Number: EP3C16F484I7N
• Description: Cyclone III
• Manufacturer: Altera

Specifications of EP3C16F484I7N

• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 15408
• # I/os (max): 346
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 15408
• Ram Bits: 516096
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / Rohs Status: Compliant

5–10
Cyclone III Device Family PLL Hardware Overview
Figure 5–6. Cyclone III Device Family PLL Block Diagram
Notes to
(1) Each clock source can come from any of the four clock pins located on the same side of the device as the PLL.
(2) This is the VCO post-scale counter K.
(3) This input port is fed by a pin-driven dedicated GCLK, or through a clock control block if the clock control block is fed by an output from another
External Clock Outputs
Cyclone III Device Handbook, Volume 1
PLL or a pin-driven dedicated GCLK. An internally generated global signal cannot drive the PLL.
pfdena
Clock inputs
Figure
GCLK
from pins
(3)
5–6:
1
4
This section gives a hardware overview of the Cyclone III device family PLL.
Figure 5–6
the Cyclone III device family.
The VCO post-scale counter K is used to divide the supported VCO range by two. The
VCO frequency reported by the Quartus II software in the PLL summary section of
the compilation report takes into consideration the VCO post-scale counter value.
Therefore, if the VCO post-scale counter has a value of 2, the frequency reported is
lower than the f
Cyclone III LS Device Data Sheet
Each PLL of the Cyclone III device family supports one single-ended clock output or
one differential clock output. Only the C0 output counter can feed the dedicated
external clock outputs, as shown in
Other output counters can feed other I/O pins through the GCLK.
inclk0
inclk1
Switchover
Clock
Block
shows a simplified block diagram of the major components of the PLL of
VCO
÷n
clkswitch
clkbad0
clkbad1
activeclock
specification specified in the
PFD
LOCK
circuit
chapters.
(Note 1)
CP
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
lock
Detector
Figure
Range
VCO
LF
VCO
5–7, without going through the GCLK.
8
VCOOVRR
VCOUNDR
no compensation;
source-synchronous;
normal mode
Cyclone III Device Data Sheet
÷2 (2)
ZDB mode
Cyclone III Device Family PLL Hardware Overview
8
© December 2009 Altera Corporation
÷M
÷C0
÷C2
÷C4
÷C1
÷C3
output
PLL
mux
GCLKs
External clock
output
GCLK
networks
and