EVAL-AD5501EBZ Analog Devices Inc, EVAL-AD5501EBZ Datasheet - Page 13

• Manufacturer Part Number: EVAL-AD5501EBZ
• Description: Evaluation Board I.c.
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5501EBZ

• Number Of Dac's: 1
• Number Of Bits: 12
• Outputs And Type: 1, Single Ended
• Sampling Rate (per Second): 16M
• Data Interface: SPI™, QSPI™, MICROWIRE™, and DSP
• Settling Time: 45µs
• Dac Type: Voltage
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 105°C
• Utilized Ic / Part: AD5501
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

THEORY OF OPERATION
The AD5501 contains a 12-bit DAC, an output amplifier, and a
precision reference in a single package. The architecture of the
DAC channel consists of a 12-bit resistor string DAC followed
by an output buffer amplifier. The part operates from a single-
supply voltage of 10 V to 62 V. The DAC output voltage range is
selected via the range select, R_SEL , pin. The DAC output range
is 0 V to 30 V if R_SEL is held high and 0 V to 60 V if R_SEL is
held low. Data is written to the AD5501 in a 16-bit word format
(see
POWER-UP STATE
On power-up, the power-on reset circuitry clears the bits of the
control register to 0x40 (see Table 10) ensuring that the analog
section is initially powered down, which helps reduce power
consumption. The user can program the DAC register to the
required value while typically consuming only 30
current. The power-on reset circuitry also ensures that the input
and DAC registers power up in a known condition, 0x000, and
remain there until a valid write to the device has taken place.
The analog section can be powered up by setting Bit C2 of the
control register to 1.
POWER-DOWN MODE
The DAC channel can be powered up or powered down by
programming Bit C2 in the control register (see Table 10).
When the DAC channel is powered down, the associated analog
circuitry turns off to reduce power consumption. The digital
section of the AD5501 remains powered up. The output of the
DAC amplifier can be three-stated or connected to AGND via
an internal 20 kΩ resistor, depending on the state of Bit C6 in
the control register. The power-down mode does not change
the contents of the DAC register to ensure that the DAC channel
returns to its previous voltage when the power-down bit is set
to 1. The AD5501 also offers the user the flexibility of updating
the DAC registers during power-down. The control register can
be read back at any time to check the status of the bits.
DAC CHANNEL ARCHITECTURE
The architecture of the DAC channel consists of a 12-bit resistor
string DAC followed by an output buffer amplifier (see Figure 14).
The resistor string section is simply a string of resistors, each of
Value R from V
This type of architecture guarantees DAC monotonicity. The
12-bit binary digital code loaded to the DAC register determines at
which node on the string the voltage is tapped off before being
fed into the output amplifier. The output amplifier multiplies
the DAC output voltage to give a fixed linear voltage output
range of 0 V to 60 V if R_SEL = 0 or 0 V to 30 V if R_SEL = 1.
Each output amplifier is capable of driving a 60 kΩ load while
allowing an output swing within the range of AGND + 0.5 V to
V
Because the DAC architecture gives a fixed voltage output range
of 0 V to 30 V or 0 V to 60 V, the user should set V
30.5 V or 60.5 V to use the maximum DAC resolution. The data
DD
− 0.5 V.
Table 8
), via a serial interface.
REF
generated by the precision reference to AGND.
μ
DD
A of supply
to at least
Rev. A | Page 13 of 20
format for the AD5501 is straight binary and the output voltage
follows the formula
where:
D is the code loaded to the DAC.
Range = 30, if R_SEL is high, and 60 if R_SEL is low.
V
The voltage feedback pin (V
the gain amplifier. To compensate for any voltage drop between
the V
tion) V
The V
more current is required than can be supplied by the AD5501.
The configuration is shown in Figure 16.
SELECTING THE OUTPUT RANGE
The output range of the DAC is selected by the R_SEL pin.
When the R_SEL pin is connected to a Logic 1, the DAC output
voltage can be set between 0 V and 30 V. When the R_SEL pin
is connected to a Logic 0, the DAC output voltage can be set
between 0 V and 60 V. The state of R_SEL can be changed any
time when the serial interface is not being used, that is, not
during a read or write operation. When the R_SEL pin is
FB
REGISTER
PIN
V
OUT
INPUT
FB
OUT
FB
pin can also be used to control a pass transistor where
pin and the load, connect (in a force sense configura-
to the V
=
4096
D
12
Figure 16. Pass Transistor Configuration
12-BIT
12-BIT
DAC
Figure 15. V
122.36kΩ
Figure 14. DAC Channel Architecture
DAC
OUT
128kΩ
×
REGISTER
Range
pin, as shown in Figure 15.
DAC
FB
FB
and V
OUTPUT
BUFFER
OUTPUT
) is part of the feedback loop of
BUFFER
12
REFERENCE
OUT
2432kΩ
PRECISION
1713kΩ
AGND
Configuration
DAC
V
V
V
V
OUT
FB
OUT
FB
GAIN
V
DD
AD5501
R
R
L
L
V
OUT