EVAL-AD5501EBZ Analog Devices Inc, EVAL-AD5501EBZ Datasheet - Page 9

• Manufacturer Part Number: EVAL-AD5501EBZ
• Description: Evaluation Board I.c.
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5501EBZ

• Number Of Dac's: 1
• Number Of Bits: 12
• Outputs And Type: 1, Single Ended
• Sampling Rate (per Second): 16M
• Data Interface: SPI™, QSPI™, MICROWIRE™, and DSP
• Settling Time: 45µs
• Dac Type: Voltage
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 105°C
• Utilized Ic / Part: AD5501
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 7. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9, 10
11
12
13
14
15
16
Mnemonic
CLR
SYNC
SCLK
SDI
SDO
DGND
AGND
LDAC
NC
V
V
R_SEL
V
ALARM
V
FB
OUT
DD
LOGIC
Description
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored.
When CLR is activated, the input register and the DAC register are set to 0x000 and the output to zero scale.
Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC goes
low, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The
selected DAC register is updated following the 16th clock cycle, unless SYNC is taken high before this edge, in
which case the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates of up to 16 MHz.
Serial Data Input. This part has a 16-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
Serial Data Output. CMOS output. This pin serves as the readback function for all DAC and control registers. Data is
clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK.
Digital Ground Pin.
Analog Ground Pin.
Load DAC Input. Pulsing this pin low updates the DAC with the value in the input register. If the LDAC pin is tied
low, the DAC output is updated automatically when data is written to the input register.
Not Connected. These pins remain unconnected.
Voltage Feedback Pin. Feedback node for the output amplifier.
Buffered Analog Output Voltage from the DAC.
Range Select Pin. Tying this pin to DGND selects a DAC output range of 0 V to 60 V, alternatively tying R_SEL to
V
Positive Analog Power Supply. 10 V to 62 V for the specified performance. Decouple this pin with 0.1μF ceramic
capacitors and 10 μF capacitors.
Active Low CMOS Output Pin. Flags an alarm if the temperature on the die exceeds 110°C.
Logic Power Supply; 2.3 V to 5.5 V. Decouple this with 0.1 μF ceramic capacitors and 10 μF capacitors.
LOGIC
selects a DAC output range of 0 V to 30 V.
DGND
A
SYNC
LDAC
SCLK
GND
SDO
CLR
SDI
Figure 5. TSSOP Configuration
1
2
3
4
5
6
7
8
NC = NO CONNECT
Rev. A | Page 9 of 20
(Not to Scale)
AD5501
TOP VIEW
16
15
14
13
12
11
10
9
V
ALARM
V
R_SEL
V
V
NC
NC
LOGIC
DD
OUT
FB
AD5501