EVAL-AD5501EBZ Analog Devices Inc, EVAL-AD5501EBZ Datasheet - Page 6

• Manufacturer Part Number: EVAL-AD5501EBZ
• Description: Evaluation Board I.c.
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5501EBZ

• Number Of Dac's: 1
• Number Of Bits: 12
• Outputs And Type: 1, Single Ended
• Sampling Rate (per Second): 16M
• Data Interface: SPI™, QSPI™, MICROWIRE™, and DSP
• Settling Time: 45µs
• Dac Type: Voltage
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 105°C
• Utilized Ic / Part: AD5501
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5501
TIMING CHARACTERISTICS
V
Table 4.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
Circuit and Timing Diagrams
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V
Maximum SCLK frequency is 16.667 MHz.
Under the load conditions that are outlined in Figure 2.
Time from when V
Time required from execution of power-on software command to when the DAC output has settled to 1 V.
DD
2
3
3
4
5
= 30 V, V
LOGIC
DD
or V
= 2.3 V to 5.5 V, and −40°C < T
LOGIC
Limit
60
10
10
30
15
5
0
20
20
50
15
100
20
110
55
25
50
50
5
supplies are powered-up to when a digital interface command can be executed.
1
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
μs typ
ns min
ns max
ns min
μs max
μs max
μs typ
TO OUTPUT
PIN
Figure 2. Load Circuit for SDO Timing Diagram
A
Test Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
LDAC pulse width low
SCLK falling edge to LDAC rising edge
CLR pulse width low
CLR pulse activation time
ALARM clear time
SCLK cycle time in read mode
SCLK rising edge to SDO valid
SCLK to SDO Data hold time
Power-on-reset time (this is not shown in the timing figures)
Power-on time (this is not shown in the timing figures)
ALARM clear to output amplifier turn on (this is not shown in the timing figures)
< +105°C, all specifications T
50pF
C
DD
L
) and timed from a voltage level of (V
200µA
200µA
Rev. A | Page 6 of 20
I
I
OL
OH
V
OH
(MIN) – V
MIN
2
to T
OL
IL
(MAX)
MAX
+ V
IH
, unless otherwise noted.
)/2.