KSZ8842-16MBL Micrel Inc, KSZ8842-16MBL Datasheet - Page 49

• Manufacturer Part Number: KSZ8842-16MBL
• Description: 2-Port Ethernet Switch/Repeater + Generic (8, 16-bit) Bus Interface ( )
• Manufacturer: Micrel Inc

Specifications of KSZ8842-16MBL

• Controller Type: Ethernet Switch Controller
• Interface: PCI
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFBGA
• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog/Digital
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.5V
• Operating Supply Voltage (min): 3.1V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1635 - BOARD EVALUATION KSZ8842-16MVL576-1634 - BOARD EVALUATION KSZ8842-16MQL
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-3076

The format for ConfigParam is shown in Table 13.
Loopback Support
The KSZ8842M provides loopback support for remote diagnostic of failure. In loopback mode, the speed at both PHY
ports will be set to 100BASE-TX full-duplex mode. Two types of loopback are supported: Far-end Loopback and Near-end
(Remote) Loopback.
Far-end Loopback
Far-end loopback is conducted between the KSZ8842M’s two PHY ports. The loopback path starts at the “Originating.”
PHY port’s receive inputs (RXP/RXM), wraps around at the “loopback” PHY port’s PMD/PMA, and ends at the
“Originating” PHY port’s transmit outputs (TXP/TXM).
Bit [8] of registers P1CR4 and P2CR4 is used to enable far-end loopback for ports 1 and 2, respectively. Alternatively, Bit
[14] of registers P1MBCR and P2MBCR can also be used to enable far-end loopback. The port 2 far-end loopback path is
illustrated in the Figure 15.
Near-end (Remote) Loopback
Near-end (Remote) loopback is conducted at either PHY port 1 or PHY port 2 of the KSZ8842M. The loopback path starts
at the PHY port’s receive inputs (RXPx/RXMx), wraps around at the same PHY port’s PMD/PMA, and ends at the PHY
port’s transmit outputs (TXPx/TXMx).
Bit [1] of registers P1PHYCTRL and P2PHYCTRL is used to enable near-end loopback for ports 1 and 2, respectively.
Alternatively, Bit [9] of registers P1SCSLMD and P2SCSLMD can also be used to enable near-end loopback. The both
ports 1 and 2 near-end loopback paths are illustrated in the following Figure 16.
Micrel, Inc.
October 2007
Bit
15 -2
1
0
Bit Name
Reserved
Clock_Rate
ASYN_8bit
Description
Reserved
Internal clock rate selection
0: 125 MHz
1: 25 MHz
Note: At power up, this chip operates on 125 MHz clock. The internal frequency can be
dropped to 25 MHz via the external EEPROM.
Async 8-bit or 16-bit bus select
1= bus is configured for 16-bit width
0= bus is configured for 8-bit width
(32-bit width, KSZ8842-32, don’t care this bit setting)
Table 13. ConfigParam Word in EEPROM Format
49
KSZ8842-16/32 MQL/MVL/MVLI/MBL
M9999-102207-1.9