UDA1341TSDB NXP Semiconductors, UDA1341TSDB Datasheet - Page 7

• Manufacturer Part Number: UDA1341TSDB
• Description: Audio CODECs AUDIO CODEC MINIDISC
• Manufacturer: NXP Semiconductors

Specifications of UDA1341TSDB

• Number Of Adc Inputs: 4
• Number Of Dac Outputs: 2
• Conversion Rate: 48 KSPs
• Interface Type: Serial (I2S), L3
• Resolution: 20 bit
• Operating Supply Voltage: 2.4 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Minimum Operating Temperature: - 20 C
• Number Of Channels: 2
• Snr: 100 dB
• Supply Current: 12.5 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: UDA1341TS/N1,512

NXP Semiconductors
7
7.1
The UDA1341TS accommodates slave mode only, this
means that in all applications the system devices must
provide the system clock. The system frequency is
selectable. The options are 256f
The system clock must be locked in frequency to the digital
interface signals.
7.2
The UDA1341TS is partially pin compatible with the
UDA1340M and UDA1344TS, making an upgrade of a
printed-circuit board from UDA1340M to UDA1341TS
easier. The pins that are compatible with the UDA1340M
are marked in Fig.3.
7.3
The analog front end of the UDA1341TS consists of two
stereo ADCs with a Programmable Gain Amplifier (PGA) in
channel 2. The PGA is intended to pre-amplify a
microphone signal applied to the input channel 2.
Input channel 1 has a selectable 0 or 6 dB gain stage, to
be controlled via the L3-interface. In this way, input signals
of 1 V (RMS value) or 2 V (RMS value) e.g. from a
CD source can be supported using an external resistor of
12 kΩ in series with the input channel 1. The application
modes are given in Table 1.
Table 1 Application modes using input gain stage
Note
1. If there is no need for 2 V (RMS value) input signal
7.4
The PGA can be set via the L3-interface at the gain
settings: −3, 0, 3, 9, 15, 21 or 27 dB.
2002 May 16
Present
Present
Absent
Absent
RESISTOR
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
(12 kΩ)
support, the external resistor should not be used.
FUNCTIONAL DESCRIPTION
System clock
Pin compatibility
Analog front end
Programmable Gain Amplifier (PGA)
0 dB
6 dB
0 dB
6 dB
SWITCH
INPUT
GAIN
2 V (RMS value) input signal;
note 1
1 V (RMS value) input signal
1 V (RMS value) input signal
0.5 V (RMS value) input signal
MAXIMUM INPUT VOLTAGE
s
, 384f
s
or 512f
s
.
7
7.5
The stereo ADC of the UDA1341TS consists of two
3rd-order Sigma-Delta modulators. They have a modified
Ritchie-coder architecture in a differential switched
capacitor implementation. The over-sampling ratio is 128.
7.6
Input channel 2 has a digital AGC to compress the
dynamic range when a microphone signal is applied to
input channel 2. The digital AGC can be switched on and
off via the L3-interface. In the on state the AGC
compresses the dynamic range of the input signal of input
channel 2. Via the L3-interface the user can set the
parameters of the AGC: attack time, decay time and output
level. When the AGC is set off via the L3-interface, the gain
of input channel 2 can be set manually. In this case the
gain of the PGA and digital AGC are combined. The range
of the gain of the input channel 2 is from −3 to +60.5 dB in
steps of 0.5 dB.
7.7
The AGCSTAT signal from the digital AGC is HIGH when
the gain level of the AGC is below 8 dB. This signal can be
used to give the PGA a new gain setting via the
L3-interface and to power e.g. a LED.
7.8
The two stereo ADCs (including the AGC) can be used in
four modes:
• ADC1 only mode (for line input); input channel 2 is off
• ADC2 only mode, including PGA and digital AGC (for
• ADC1 + ADC2 mixer mode, including PGA and AGC
• ADC1 and ADC2 double differential mode (improved
Important: In order to prevent crosstalk between the line
inputs no signal should be applied to the microphone input
in the double differential mode.
In all modes (except the double differential mode) a
reference voltage is always present at the input of the
ADC. However, in the double differential mode there is no
reference voltage present at the microphone input.
In the mixer mode, the output signals of both ADCs in
channel 1 and channel 2 (after the digital AGC) can be
mixed with coefficients that can be set via the L3-interface.
The range of the mixer coefficients is from 0 to −∞ dB in
1.5 dB steps.
microphone input); input channel 1 is off
ADC performance).
Digital Automatic Gain Control (AGC)
AGC status detection
Digital mixer
Analog-to-Digital Converter (ADC)
UDA1341TS
Product specification