MAX9485ETP Maxim Integrated Products, MAX9485ETP Datasheet - Page 10

• Manufacturer Part Number: MAX9485ETP
• Description: Clock Generators & Support Products Programmable Audio C lock Generator Gener
• Manufacturer: Maxim Integrated Products

In software mode, the I
8-bit control register in the MAX9485. The control regis-
ter controls the rate settings and the clock outputs.
Since there is only one register in the MAX9485, no
address is assigned to this register. The device has a
programmable 7-bit address for the I
by SAO1 and SAO2 (Table 8). At power-up with MODE
= low, the MAX9485 reads the state of SAO1 and
SAO2, then latches the I
shows the control register bit mapping. Bit C7 enables
the MCLK output. Bits C5 and C6 enable the clock out-
puts CLK_OUT1 and CLK_OUT2, respectively. Bit C4
selects the sampling rates. Bits C3 and C2 choose the
output frequency-scaling factor. Bits C1 and C0 deter-
mine the sampling frequency. The details are shown in
Tables 10–14.
The MAX9485 control interface uses a 2-wire I
interface. The device operates as a slave that sends
and receives data through clock line SCL and data line
SDA to achieve bidirectional communication with the
master. A master (typically a microcontroller) initiates all
data transfers to and from the MAX9485, and generates
the SCL clock that synchronizes the data transfer. The
Programmable Audio Clock Generator
Table 5. Selection of Sampling Frequency
Table 6. MCLK Enable/Disable Control
Table 7. CLK_OUT Enable/Disable Control
10
High/low
High/low
High/low
SAO1
______________________________________________________________________________________
SAO1
Open
Open
High
High
FS0
Low
Low
SAO2
Open
High
Low
Software Mode Programming
SAMPLING FREQUENCY (kHz)
2
C interface writes or reads an
2
CLK_OUT1
C device address. Table 9
Disabled
Enabled
Enabled
Reserved
Disabled
Enabled
MCLK
44.1
32
48
Serial Interface
(MODE = Low)
2
C bus, selected
CLK_OUT2
Disabled
Enabled
Enabled
2
C serial
Table 8. Register Address Selection
Table 9. Control Register Bit Mapping
Table 10. MCLK Enable/Disable Control
Table 11. CLK_OUT1, 2 Enable/Disable
Control
Table 12. Sampling Rate Selection
C6, C5
C3, C2
C1, C0
BIT
C7
C4
C6
SAO1
1
1
0
0
Open
Open
Open
High
High
High
Low
Low
Low
C7
0
1
C4
0
1
MCLK enable/disable
CLK_OUT2, CLK_OUT1 enable/disable
Sampling-rate selection
Frequency-scaling factors
Sampling-frequency selection
C5
1
0
1
0
SAO2
Open
Open
Open
High
High
High
Low
Low
Low
CLK_OUT2
Disabled
Disabled
Enabled
Enabled
FUNCTION
SAMPLING RATE
Disabled
Enabled
Standard
MCLK
Doubled
I
2
C DEVICE ADDRESS
110 0000
110 0011
110 0010
110 0100
110 1000
111 0000
111 0001
111 0010
111 0100
CLK_OUT1
Disabled
Disabled
Enabled
Enabled