MAX9485ETP Maxim Integrated Products, MAX9485ETP Datasheet - Page 6

• Manufacturer Part Number: MAX9485ETP
• Description: Clock Generators & Support Products Programmable Audio C lock Generator Gener
• Manufacturer: Maxim Integrated Products

Programmable Audio Clock Generator
6
10, 11, 15
TSSOP
6, 17
_______________________________________________________________________________________
12
13
14
16
18
19
—
20
1
2
3
4
5
7
8
9
PIN
Exposed
8, 9, 13
TQFN
4, 15
Pad
19
20
10
11
12
14
16
17
18
1
2
3
5
6
7
CLK_OUT1
CLK_OUT2
SCL/FS0
SDA/FS1
GND_P
NAME
MODE
V
MCLK
SAO1
SAO2
GND
TUN
V
FS2
RST
DD_P
X1
X2
EP
DD
PLL Power Supply. Bypass V
PLL Ground
VCXO Tuning Voltage Input. Apply 0 to 3V at TUN to adjust the VCXO frequency. Connect
TUN to V
Crystal Connection 1. Connect a fundamental mode crystal between X1 and X2 for use as a
VCXO, or drive X1 directly with a 27MHz input reference clock.
Crystal Connection 2. Connect a fundamental mode crystal between X1 and X2 for use as a
VCXO, or leave X2 unconnected when driving X1 with a 27MHz system reference clock.
Digital Power Supply. Bypass V
Serial Clock/Function Selection Input 0. When MODE = low, SCL/FS0 functions as the I
serial clock input. When MODE = high, SCL/FS0 functions as a three-level input to select
sampling frequency.
Serial Data I/O/Function Selection Input 1. When MODE = low, SDA/FS1 functions as the I
serial data input/output. When MODE = high, SDA/FS1 functions as a three-level input to
select output frequency scaling factor.
Function Selection Input 2. When MODE = high, FS2 functions as a three-level input to select
sampling rate. When MODE = low, voltage levels at FS2 do not affect device operation.
Ground
Reset Input. Drive RST low resets the I
to V
Mode Control Input. When MODE = low, the I
hardwired interface is active, and function selection is programmed by SCL/FS0, SDA/FS1,
and FS2. Mode is internally pulled to GND.
Output Clock Port 1. CLK_OUT1 operates at 256/384/768f
selection. CLK_OUT1 is pulled low when disabled.
Output Clock Port 2. CLK_OUT2 operates at 256/384/768f
selection. CLK_OUT2 is pulled low when disabled.
Master System Clock Buffered Output. MCLK outputs the 27MHz clock generated by the
internal VCXO. MCLK is pulled low when disabled.
I
When MODE = low, SAO1 is a three-level I
MODE = high, SAO1 controls MCLK enable/disable.
I
= low, SAO2 is a three-level I
SAO2 controls CLK_OUT1 and CLK_OUT2 enable/disable.
Exposed Pad. Connect EP to ground.
2
2
C Device Address Selection Input 1 or MCLK Output Enable Control Input.
C Device Address Selection Input 2 or CLK_OUT Output Enable Control Input. When MODE
DD
.
DD
when driving X1 directly with a 27MHz input reference clock.
DD_P
2
C device address programming input. When MODE = high,
DD
with a 0.1µF and 0.001µF capacitor to GND_P.
with a 0.1µF and 0.001µF capacitor to GND.
2
C register to its default state. RST is internally pulled
FUNCTION
2
C device address programming input. When
2
C interface is active. When MODE = high, the
s
s
, depending on the function
, depending on the function
Pin Description
2
C
2
C