MAX9485ETP Maxim Integrated Products, MAX9485ETP Datasheet - Page 9

• Manufacturer Part Number: MAX9485ETP
• Description: Clock Generators & Support Products Programmable Audio C lock Generator Gener
• Manufacturer: Maxim Integrated Products

The internal power-on reset completes after 1024
cycles of the reference clock starting when V
greater than 2.2V with a tolerance of ±0.4V. When
using the internal power-on reset, RST must be high.
Figure 3 shows power-on reset timing. The internal
reset function also accepts an external forced reset by
driving RST = low. The reset is triggered when RST =
low and completes after 1024 reference clock cycles.
When a reset is initiated, any pulses on RST during the
1024 reference clock cycles are ignored. If RST is held
low at the end of a reset cycle, reset does not initiate
until a high-to-low transition is detected at RST. Figure
4 shows external reset timing.
Figure 3. Power-On Reset Timing
Figure 4. External Reset Timing
INTERNAL
INTERNAL
RESET
RESET
2.2V
1.8V
2.6V
RST
V
DD
_______________________________________________________________________________________
1024 CYCLES AT 27MHz
(MIN: 20ns)
RESET PERIOD =
POWER-ON RESET RANGE
1024 CYCLES AT 27MHz
Programmable Audio Clock Generator
RESET PERIOD =
RESET
REMOVAL
RESET
REMOVAL
DD
is
The MAX9485 sampling frequency, sampling rate, and
clock outputs can be programmed through the I
2-wire interface (software mode, MODE = low), or
hardwired directly through three-level inputs (hardwire
mode, MODE = high). The offered functions for each
mode are shown in Table 2. CLK_OUT and MCLK are
pulled low when disabled.
In hardwire mode, FS2 selects the sampling rate (Table
3). With FS2 = low, the sampling rate is standard. With
FS2 = high, the sampling rate is doubled. When FS2 =
open, the 12kHz standard rate is selected, overriding
the setting of FS0. FS1 selects the scaling factors: 256,
384, and 768 (Table 4). FS0 selects the sample
frequencies: 32kHz, 44.1kHz, and 48kHz (Table 5).
When MODE = high, inputs SAO1 and SAO2 enable or
disable the clock outputs (Tables 6 and 7). CLK_OUT
and MCLK are pulled low when disabled.
Table 2. Selectable Functions
Table 3. Sampling Rate Selection
Table 4. Frequency Scaling Factors
Standard sampling
frequencies:
12kHz, 32kHz,
44.1kHz, 48kHz
Double sampling
frequencies:
64kHz, 88.2kHz, 96kHz
CLK_OUT1, CLK_OUT2,
MCLK:
enable/disable
Open
Open
High
High
FS1
Low
FS2
Low
FUNCTIONS
Software and Hardwire Control Modes
Standard (32kHz, 44.1kHz, 48kHz)
Doubled (64kHz, 88.2kHz, 96kHz)
Standard (12kHz)
Hardwire Mode Programming
OUTPUT SCALING FACTOR
MODE = HIGH
HARDWIRE
SAMPLING RATE
MODE
✓
✓
✓
256
384
768
(MODE = High)
MODE = LOW
SOFTWARE
MODE
✓
✓
✓
2
C
9