MAX9485ETP Maxim Integrated Products, MAX9485ETP Datasheet - Page 7

• Manufacturer Part Number: MAX9485ETP
• Description: Clock Generators & Support Products Programmable Audio C lock Generator Gener
• Manufacturer: Maxim Integrated Products

The MAX9485 uses an input reference frequency of
27MHz from a crystal or system reference clock. The
device provides two buffered clock outputs of 256, 384,
or 768 times the chosen sampling frequency (f
ed through an I
Sampling frequencies of 12kHz, 32kHz, 44.1kHz,
48kHz, 64kHz, 88.2kHz, or 96kHz are available. The
MAX9485 offers a buffered 27MHz output and an inte-
grated VCXO tuned by a DC voltage generated from the
MPEG system. The device operates with a 3.3V supply.
The MAX9485 uses the 27MHz crystal or reference
clock (master clock) from the audio system and gener-
ates an output of 256, 384, or 768 times the audio sys-
tem sampling frequency (f
MODE
TUN
RST
X1
X2
2
_______________________________________________________________________________________
Reference and Output Clock
C interface or hardwired inputs.
Detailed Description
RESET
Programmable Audio Clock Generator
VCXO
S
). Connect a fundamental
COUNTER M
COUNTER N
V
DD
GND
S
DETECTOR
AND LOOP
) select-
PHASE
FILTER
V
REGISTERS
CONTROL
DD_P
mode crystal between X1 and X2 or drive X1 with a
27MHz system clock. The choices of sampling frequen-
cies are 12kHz, 32kHz, 44.1kHz, 48kHz, 64kHz,
88.2kHz, and 96kHz. The MAX9485 offers two identical
outputs: CLK_OUT1 and CLK_OUT2. In the following,
the CLK_OUT is used to refer to both outputs. Table 1
shows the relations of f
Select the output frequency by programming the I
register or hardwiring inputs FS0, FS1, and FS2.
CLK_OUT settling is typically 15ms from power-on or
from applying the clock to X1. Delay time from sampling
frequency change to CLK_OUT settling is 10ms (typ).
Figure 1 illustrates CLK_OUT transient timing in the I
programmed case. The I
master-write data transfer. The frequency settling time
t
the written byte in SDA until the CLK_OUT is settled.
VCO
FST
SAO1 SAO2
PLL
is counted from the end of the next ACK pulse of
COUNTER
DIVIDING
MAX9485
Functional Diagram
GND_P
S
2
and the output frequency.
C register is set through a
MCLK
CLK_OUT1
CLK_OUT2
SCL/FS0
SDA/FS1
FS2
2
2
C
C
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