MAX9485ETP Maxim Integrated Products, MAX9485ETP Datasheet - Page 11

• Manufacturer Part Number: MAX9485ETP
• Description: Clock Generators & Support Products Programmable Audio C lock Generator Gener
• Manufacturer: Maxim Integrated Products

Table 13. Frequency Scaling Factors
Table 14. Sampling Frequency Selection
Note: (C1, C0) = (0, 0) and C4 = 1 (double) is not a proper selec-
tion. However, when set, it selects 12kHz sampling frequency.
SDA line operates as both an input and an open-drain
output. A pullup resistor, typically 4.7kΩ, is required on
SDA. The SCL line operates only as an input. A pullup
resistor, typically 4.7kΩ, is required on SCL if there are
multiple masters on the 2-wire bus, or if the master in a
single-master system has an open-drain SCL output.
Both SCL and SDA remain high when the interface is
idle. The active master signals the beginning of a trans-
mission with a START (S) condition by transitioning
SDA from high to low while SCL is high. After communi-
cation, the MAX9485 issues a STOP (P) condition by
transitioning SDA from low to high while SCL is high,
freeing the bus for another transmission (Figure 5). If a
START or STOP occurs while a bus transaction is in
progress, then it terminates the transaction.
Following the START condition, each SCL clock pulse
transfers 1 bit. For the MAX9485 interface, between a
START and a STOP, 18 bits are transferred on the
2-wire bus. The first 7 bits are for the device address.
Bit 8 indicates the writing (low) or reading (high) opera-
tion (R/W). Bit 9 is the ACK for the address and opera-
tion type. Bits 10 though 17 form the data byte. Bit 18 is
the ACK for the data byte. The master always transfers
C1
0
0
1
1
C3
0
0
1
1
Data Transfer and Acknowledge
C0
0
1
0
1
C2
______________________________________________________________________________________
0
1
0
1
Start and Stop Conditions
Programmable Audio Clock Generator
SAMPLING FREQUENCY (kHz)
OUTPUT SCALING FACTOR
Reserved
44.1
12
32
48
256
384
768
the first 8 bits (address + R/W). The slave (MAX9485)
can receive the data byte from the bus or transfer it to
the bus from the internal register. The ACK bits are
transmitted by the address or data recipient. A low
ACK bit indicates a successful transfer (Acknowledge),
a high ACK bit indicates an unsuccessful transfer (Not
Acknowledge). Figure 6 shows the structure of the data
transfer. During a write operation, if more synchronous
data is transferred, it overwrites the data in the register.
During a read operation, if more clocks are reset on
SCL, the SDA continues to respond to the register data.
Figure 5. Start and Stop Conditions
Figure 6. Serial Interface Data Structure
SDA
SCL
A = ACK; A = 0: ACKNOWLEDGE, A = 1: NOT ACKNOWLEDGE
S = START CONDITION
P = STOP CONDITION
S
S
CONDITION
START
MASTER TRANSFERS TO SLAVE
SLAVE TRANSFERS TO MASTER
S
SLAVE ADDRESS
SLAVE ADDRESS
7 BITS
7 BITS
MASTER-WRITE DATA STRUCTURE
MASTER-READ DATA STRUCTURE
R/W
R/W
A
A
8 BITS
8 BITS
DATA
DATA
CONDITION
STOP
A
A
P
P
P
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