ISP1505ABS NXP Semiconductors, ISP1505ABS Datasheet - Page 22

• Manufacturer Part Number: ISP1505ABS
• Description: RF Transceiver USB2.0/ULPI1.1 XCVR
• Manufacturer: NXP Semiconductors

Specifications of ISP1505ABS

• Number Of Receivers: 5
• Number Of Transmitters: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: HVQFN-24
• Maximum Data Rate: 480 Mbps
• Maximum Supply Current: 0.001 mA, 48 mA
• Minimum Operating Temperature: - 40 C
• Protocol Supported: USB 2.0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1505ABS,557

NXP Semiconductors
ISP1505A_ISP1505C_3
Product data sheet
Fig 5.
DATA[7:0]
RESET_N
CLOCK
NXT
STP
DIR
Interface behavior with respect to RESET_N
9.3.2 Interface behavior with respect to RESET_N
9.4.1 Driving 5 V on V
9.4.2 Fault detection
9.4 V
Hi-Z (input)
Hi-Z (input)
The interface protect feature can be disabled by setting the INTF_PROT_DIS bit to logic 1.
The use of the RESET_N pin is optional. When RESET_N is asserted (LOW), the
ISP1505 will assert DIR. All logic in the ISP1505 will be reset, including the analog
circuitry and ULPI registers. During reset, the link must drive DATA[7:0] and STP to LOW;
otherwise undefined behavior may result. When RESET_N is deasserted (HIGH), the DIR
output will deassert (LOW) four or five clock cycles later.
interface behavior when RESET_N is asserted (LOW), and subsequently deasserted
(HIGH). If RESET_N is not used, it must be connected to V
The ISP1505 supports external 5 V supplies. The ISP1505 can control the external supply
using the active-LOW PSW_N open-drain output pin. To enable the external supply by
driving PSW_N to LOW, the link must set the DRV_VBUS_EXT bit in the OTG Control
register to logic 1. When the DRV_VBUS_EXT bit is set, the DRV_VBUS bit can be set to
any value and will be ignored.
The ISP1505 supports external V
circuit is required for host applications that supply more than 100 mA on V
between 4.75 V to 5.25 V. For low-power applications supplying less than 100 mA, the
V
link can utilize the internal A_VBUS_VLD comparator.
The ISP1505 supports external V
indicator signal. The indicator signal must be connected to the V
the ISP1505 to monitor the digital fault input, the link must set the USE_EXT_VBUS_IND
bit in the OTG Control register and the IND_PASSTHRU bit in the Interface Control
register to logic 1. For details, see
BUS
BUS
power line can directly be connected to the V
power and fault detection
Hi-Z (link must drive)
Hi-Z (link must drive)
BUS
Rev. 03 — 26 August 2008
BUS
BUS
Figure
fault detector circuits. An overcurrent detection
fault detector circuits that output a digital fault
ULPI HS USB host and peripheral transceiver
Hi-Z (input)
7.
Hi-Z (input)
ISP1505A; ISP1505C
BUS
/FAULT pin on the ISP1505 and the
Figure 5
CC(I/O)
BUS
.
shows the ULPI
/FAULT pin. To enable
© NXP B.V. 2008. All rights reserved.
BUS
for voltages
004aaa720
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