MT46V16M16CY-6 IT:K Micron Technology Inc, MT46V16M16CY-6 IT:K Datasheet - Page 70

• Manufacturer Part Number: MT46V16M16CY-6 IT:K
• Description: DRAM Chip DDR SDRAM 256M-Bit 16Mx16 2.5V 60-Pin FBGA Tray
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V16M16CY-6 IT:K

• Density: 256 Mb
• Maximum Clock Rate: 333 MHz
• Package: 60FBGA
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 2.5 V
• Maximum Random Access Time: 0.7 ns
• Operating Temperature: -40 to 85 °C
• Organization: 16Mx16
• Address Bus: 15b
• Access Time (max): 700ps
• Operating Supply Voltage (typ): 2.5V
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Supply Current: 270mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Figure 33:
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
Command
Command
Command
Address
Address
Address
READ-to-PRECHARGE
DQS
DQS
DQS
CK#
CK#
CK#
DQ
DQ
DQ
CK
CK
CK
Notes:
Bank a,
Bank a,
Bank a,
READ
READ
READ
Col n
Col n
Col n
T0
T0
T0
1. Provided
2. DO n = data-out from column n.
3. BL = 4 or an interrupted burst of 8.
4. Three subsequent elements of data-out appear in the programmed order following DO n.
5. Shown with nominal
6. READ-to-PRECHARGE equals two clocks, which allows two data pairs of data-out; it is also
7. An ACTIVE command to the same bank is only allowed if
precharge to be performed at x number of clock cycles after the READ command, where
x = BL/2.
assumed that
CL = 2
t
RAS (MIN) is met, a READ command with auto precharge enabled would cause a
NOP
NOP
NOP
T1
T1
T1
CL = 2.5
t
RAS (MIN) is met.
CL = 3
t
AC,
(a or all)
(a or all)
(a or all)
Bank a,
Bank a,
Bank a,
T2
PRE
PRE
PRE
T2
T2
t
DQSCK, and
68
DO
n
T2n
T2n
DO
n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
NOP
T3
NOP
T3
NOP
t
DQSQ.
DO
n
t RP
t RP
t RP
T3n
T3n
T3n
Transitioning Data
256Mb: x4, x8, x16 DDR SDRAM
T4
NOP
T4
T4
NOP
NOP
t
RC (MIN) is met.
T4n
©2003 Micron Technology, Inc. All rights reserved.
Bank a,
Bank a,
Bank a,
T5
T5
T5
Row
ACT
ACT
Row
ACT
Row
Don’t Care
Operations