MT46V16M16CY-6 IT:K Micron Technology Inc, MT46V16M16CY-6 IT:K Datasheet - Page 71

• Manufacturer Part Number: MT46V16M16CY-6 IT:K
• Description: DRAM Chip DDR SDRAM 256M-Bit 16Mx16 2.5V 60-Pin FBGA Tray
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V16M16CY-6 IT:K

• Density: 256 Mb
• Maximum Clock Rate: 333 MHz
• Package: 60FBGA
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 2.5 V
• Maximum Random Access Time: 0.7 ns
• Operating Temperature: -40 to 85 °C
• Organization: 16Mx16
• Address Bus: 15b
• Access Time (max): 700ps
• Operating Supply Voltage (typ): 2.5V
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Supply Current: 270mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Figure 34:
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
Command
BA0, BA1
Case 1:
Case 2:
Address
DQS
DQS
CK#
CKE
A10
DM
DQ
DQ
CK
t
t
AC (MIN) and
AC (MAX) and
Bank READ – Without Auto Precharge
t
t
IS
NOP
IS
T0
t
1
Notes:
t
IH
t
IH
DQSCK (MIN)
t
DQSCK (MAX)
t
t
Bank x
IS
IS
1. NOP commands are shown for ease of illustration; other commands may be valid at these
2. BL = 4.
3. The PRECHARGE command can only be applied at T5 if
4. Disable auto precharge.
5. “Don’t Care” if A10 is HIGH at T5.
6. DO n (or b) = data-out from column n (or column b); subsequent elements are provided in
7. Refer to Figure 35 on page 70, Figure 36 on page 71, and Figure 37 on page 72 for detailed
Row
Row
ACT
T1
t
t
times.
the programmed order.
DQS and DQ timing.
IH
IH
t
CK
t
t RAS 3
t
RCD
RC
NOP
T2
1
t
CH
t
CL
Bank x
READ
t
4
IS
Col n
T3
2
t
t
IH
LZ (MIN)
CL = 2
69
NOP
T4
t
1
RPRE
t
LZ (MIN)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RPRE
One bank
All banks
Bank x
PRE
T5
t
3
DO
t
DQSCK (MIN)
n
DQSCK (MAX)
5
t
256Mb: x4, x8, x16 DDR SDRAM
AC (MIN)
DO
t
n
AC (MAX)
T5n
t
RP
NOP
t
RAS (MIN) is met.
T6
1
Transitioning Data
t
HZ (MAX)
T6n
t
RPST
©2003 Micron Technology, Inc. All rights reserved.
t
RPST
NOP
T7
1
Operations
Bank x
Don’t Care
Row
Row
ACT
T8