PEF81902FV1.1 Lantiq, PEF81902FV1.1 Datasheet - Page 161

• Manufacturer Part Number: PEF81902FV1.1
• Manufacturer: Lantiq

Specifications of PEF81902FV1.1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

XMR
XDU
4.4.4
MASKH
Value after reset: FC
Data Sheet
1 =
Transmit Message Repeat
0 =
1 =
Transmit Data Underrun
0 =
1 =
MASKH - Mask Register HDLC
A data block of up to the defined block size (EXMR.XFBS) can be
written to the XFIFO.
A XPR interrupt will be generated in the following cases:
• after a XTF or XME command as soon as the 16 / 32 bytes in the
• after a XTF together with a XME command is issued, when the
• after reset
• after XRES
inactive
The transmission of the last frame has to be repeated because a
collision on the S bus has been detected after the 16
byte of a transmit frame.
If a XMR interrupt occurs the transmit FIFO is locked until the XMR
interrupt is read by the host (interrupt cannot be read if masked in
MASKH).
inactive
The current transmission of a frame is aborted by transmitting
seven ‘1’s because the XFIFO holds no further data. This interrupt
occurs whenever the microcontroller has failed to respond to a
XPR interrupt (ISTAH register) quick enough, after having initiated
a transmission and the message to be transmitted is not yet
complete.
If a XMR interrupt occurs the transmit FIFO is locked until the XDU
interrupt is read by the host (interrupt cannot be read if masked in
MASKH).
H
XFIFO are available and the frame is not yet complete.
whole frame has been transmitted.
write
147
Register Description
Address:
th
/32
PEF 81902
2001-11-12
nd
data
20
H