PEF81902FV1.1 Lantiq, PEF81902FV1.1 Datasheet - Page 222

• Manufacturer Part Number: PEF81902FV1.1
• Manufacturer: Lantiq

Specifications of PEF81902FV1.1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

•
Figure 80
Microprocessor Interface Timing
•
Parameter
ALE pulse width
Address setup time to ALE
Address hold time from ALE
Address latch setup time to WR, RD
Address setup time
Address hold time
ALE guard time
DS delay after R/W setup
RD pulse width
Data output delay from RD
Data hold from RD
Data float from RD
RD control interval
W pulse width
Data setup time to W x CS
Data hold time W x CS
W control interval
R/W hold from CS x DS inactive
1)
Data Sheet
control interval: t
consecutive read accesses to one of the registers ISTAU or RDS, respectively, must be longer than 330ns.
This does not limit t
instance: ISTAU -(t
A0 - A6
CS x DS
Non-Multiplexed Address Timing
RI
is minimal 70ns for all registers except ISTAU and RDS. However, the time between two
RI
RI
1)
)- ISTA -(t
of read sequences, which involve intermediate read access to other registers, as for
RI
)- ISTAS -(t
RI
)- ISTAU.
208
t
AS
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AA
AL
LA
ALS
AS
AH
AD
DSD
RR
RD
DH
DF
RI
WW
DW
WD
WI
RWD
Address
Electrical Characteristics
Limit Values
min.
20
10
10
10
10
10
10
10
80
0
70
60
10
10
70
10
t
AH
max.
80
25
PEF 81902
2001-11-12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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