PEF81902FV1.1 Lantiq, PEF81902FV1.1 Datasheet - Page 182

• Manufacturer Part Number: PEF81902FV1.1
• Manufacturer: Lantiq

Specifications of PEF81902FV1.1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

MFEN
SQX1-4
4.5.7
ISTAS
Value after reset: 00
x
LD
Data Sheet
These bits are set if an interrupt status occurs and an interrupt signal is activated if the
corresponding mask bit is set to “0”. If the mask bit is set to “1” no interrupt is generated,
however the interrupt status bit is set in ISTAS. RIC, SQC and SQW are cleared by
reading the corresponding source register S_STA, SQRR or writing SQXR,
respectively.
7
0
7
x
Multiframe Enable
Used to enable or disable the multiframe structure.
0 =
1 =
Transmitted S/Q Bits
Transmitted S bits in frames 1, 6, 11 and 16
ISTAS - Interrupt Status Register S-Transceiver
Reserved
Level Detection
0 =
1 =
MFEN
x
S/T multiframe is disabled
S/T multiframe is enabled
inactive
Any receive signal has been detected on the line. This bit is set to
“1” (i.e. an interrupt is generated if not masked) as long as any
receive signal is detected on the line.
H
0
x
0
x
read
168
SQX1
LD
SQX2
RIC
Register Description
SQX3
SQC
Address:
PEF 81902
2001-11-12
SQX4
SQW
0
0
38
H