PEF81902FV1.1 Lantiq, PEF81902FV1.1 Datasheet - Page 39

• Manufacturer Part Number: PEF81902FV1.1
• Manufacturer: Lantiq

Specifications of PEF81902FV1.1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

The internal reset sources set the MODE1 register to its reset value.
Table 8
1)
•
• C/I Code Change (Exchange Awake)
• Watchdog Timer
After the selection of the watchdog timer (RSS = ’11’) an internal timer is reset and
started. During every time period of 128 ms the microcontroller has to program the
WTC1- and WTC2 bits in the following sequence to reset and restart the watchdog timer:
Otherwise the timer expires and a WOV-interrupt (ISTA Register) together with a reset
out pulse on pin RSTO of 125 µs is generated.
Deactivation of the watchdog timer is only possible with a hardware reset (including
expiration of the watchdog timer).
As in the SCOUT-S, the watchdog timer is clocked with the IOM
only if the internal IOM
minimized in state power down.
Software Reset Register (SRES)
Several main functional blocks of the T-SMINT
setting the corresponding bit in the SRES register. This is equivalent to a hardware reset
of the corresponding functional block. The reset state is activated as long as the bit is set
to ’1’.
Data Sheet
POR/UVD can be enabled/disabled via pin VDDDET
A change in the downstream C/I channel (C/I0) generates a reset pulse of 125 µs
RSS2
Bit 1
250 µs.
0
0
1
1
RSS1
Reset Source Selection
Bit 0
1.
2.
0
1
0
1
â
WTC1
1
0
-2 clocks are active. Hence, the power consumption is
C/I Code
Change
--
--
x
/RSTO disabled (= high impedance)
WTC2
0
1
25
â
IX can be reset separately by software
Watchdog
Timer
--
--
x
Functional Description
â
-2 clocks and works
POR/UVD
RST
PEF 81902
x
x
x
2001-11-12
1)
and
t