PEF81902FV1.1 Lantiq, PEF81902FV1.1 Datasheet - Page 63

• Manufacturer Part Number: PEF81902FV1.1
• Manufacturer: Lantiq

Specifications of PEF81902FV1.1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

•
Figure 24
2.3.4
The Command/Indication channel carries real-time status information between the T-
SMINT
1) C/I0 channel lies in IOM
access protocol. In this case the arbitration is done in IOM
The C/I0 channel is accessed via register CIR0 (received C/I0 data from DD) and
register CIX0 (transmitted C/I0 data to DU). The C/I0 code is four bits long.
In the receive direction, the code from layer-1 is continuously monitored, with an interrupt
being generated any time a change occurs (ISTA.CIC).
C/I0 only: a new code must be found in two consecutive IOM
valid and to trigger a C/I code change interrupt status (double last look criterion).
In the transmit direction, the code written in CIX0 is continuously transmitted in C/I0.
2) A second C/I channel (called C/I1) lies in IOM
time status information of the on-chip S-transceiver or an external device. The C/I1
channel consists of four or six bits in each direction. The width can be changed from 4
bit to 6 bit by setting bit CIX1.CICW.
Data Sheet
â
IX and another device connected to the IOM
C/I Channel Handling
MONITOR Interrupt Structure
HDLC
MASK
WOV
MOS
CIC
TIN
INT
ST
S
U
â
-2 channel 0 and access may be arbitrated via the TIC bus
HDLC
ISTA
WOV
MOS
CIC
TIN
ST
S
U
49
â
-2 channel 1 and is used to convey real
MOCR
MRE
MIE
â
-2.
â
â
-2 channel 2.
-2 frames to be considered
Functional Description
MOSR
MDR
MER
MAB
MDA
PEF 81902
2001-11-12