PEF81902FV1.1 Lantiq, PEF81902FV1.1 Datasheet - Page 178

• Manufacturer Part Number: PEF81902FV1.1
• Manufacturer: Lantiq

Specifications of PEF81902FV1.1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

BUS
EN_ICV
L1SW
EXLP
4.5.2
S_ CONF2
Value after reset: 80
Data Sheet
Note: For the external loop the transmitter must be enabled (S_CONF2:DIS_TX = 0).
1 =
Point-to-Point / Bus Selection
0 =
1 =
Enable Far End Code Violation
0 =
1 =
Enable Layer 1 State Machine in Software
0 =
1 =
External Loop
In case the analog loopback is activated with C/I = ARL or with the LP_A bit
in the S_CMD register the loop is a
0 =
1 =
S_CONF2 - S-Transmitter Configuration Register 2
All S-transceiver functions are disabled and powered down (analog
and digital parts).
Adaptive Timing (Point-to-Point, extended passive bus).
Fixed Timing (Short passive bus), directly derived from transmit
clock.
normal operation.
ICV enabled. The receipt of at least one illegal code violation within
one multi-frame according to ANSI T1.605 is indicated by the C/I
indication ‘1011’ (CVR) in two consecutive IOM frames.
Layer 1 state machine of the T-SMINT
Layer 1 state machine is disabled. The functionality must be
realized in software.
The commands are written to register S_CMD and the status read
in the S_STA.
internal loop next to the line pins
external loop which has to be closed between SR1/SR2 and SX1/
SX2
H
read/write
164
â
IX is used.
Register Description
Address:
PEF 81902
2001-11-12
32
H