SLXT973QCA3V Cortina Systems Inc, SLXT973QCA3V Datasheet - Page 81

• Manufacturer Part Number: SLXT973QCA3V
• Manufacturer: Cortina Systems Inc

Specifications of SLXT973QCA3V

• Lead Free Status / RoHS Status: Not Compliant

Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
Figure 31. 10BASE-T Transmit Timing (Parallel Mode)
Table 44. MII - 10BASE-T Transmit Timing Parameters (Parallel Mode)
TXD, TXEN, TXER setup to
TXCLK High
TXD, TXEN, TXER hold from
TXCLK High
TXEN sampled to CRS asserted
TXEN sampled to CRS
de-asserted
TXEN sampled to twisted-pair
output (Tx latency)
1. Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to
Twisted-Pair
NOTE: Twisted-pair output default pins are as follows: DPAP/N_0 and DPBP/N_1.
production testing.
TXCLK
Output
TXEN,
TXER
TXD,
CRS
Parameter
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
t
1
t
3
Sym
t1
t2
t3
t4
t5
t
5
Min
10
0
–
–
–
Typ
575
5.5
–
–
5
1
t
2
Max
–
–
–
–
–
t
4
Units
BT
BT
ns
ns
ns
Conditions
Test
–
–
–
–
–
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