MCP4706A0T-E/CH Microchip Technology, MCP4706A0T-E/CH Datasheet - Page 70

• Manufacturer Part Number: MCP4706A0T-E/CH
• Description: Single, 8-bit NV DAC With Ext Vref And I2C Interface 6 SOT-23 T/R
• Manufacturer: Microchip Technology
• Series: -r

Specifications of MCP4706A0T-E/CH

• Number Of Converters: 1
• Conversion Rate: 1
• Resolution: 8 bit
• Interface Type: I2C
• Settling Time: 6 us
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-23-6
• Maximum Power Dissipation: 452 mW
• Minimum Operating Temperature: - 40 C
• Supply Current: 210 uA
• Number Of Bits: 8
• Data Interface: EEPROM, I²C, Serial
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 452mW
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Outputs And Type: *
• Lead Free Status / Rohs Status: Details

MCP4706/4716/4726
8.9
At times, it may become necessary to perform a
Software Reset Sequence to ensure the MCP47X6
device is in a correct and known I
This technique only resets the I
This is useful if the MCP47X6 device powers up in an
incorrect state (due to excessive bus noise, etc), or if
the Master Device is reset during communication.
Figure 8-9
software reset the device.
FIGURE 8-9:
Format.
The 1st Start bit will cause the device to reset from a
state in which it is expecting to receive data from the
Master Device. In this mode, the device is monitoring
the data bus in Receive mode and can detect if the
Start bit forces an internal Reset.
DS22272A-page 70
Start
bit
Note:
S
‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’
Software I
Sequence
This technique is documented in AN1028.
shows the communication sequence to
Nine bits of ‘1’
2
Software Reset Sequence
C Interface Reset
Stop bit
Start bit
2
C state machine.
2
C Interface state.
S
P
The nine bits of ‘1’ are used to force a Reset of those
devices that could not be reset by the previous Start bit.
This occurs only if the MCP47X6 is driving an A bit on
the I
command) and is driving a data bit of ‘0’ onto the I
bus. In both of these cases, the previous Start bit could
not be generated due to the MCP47X6 holding the bus
low. By sending out nine ‘1’ bits, it is ensured that the
device will see an A bit (the Master Device does not
drive the I
the MCP47X6), which also forces the MCP47X6 to
reset.
The 2nd Start bit is sent to address the rare possibility
of an erroneous write. This could occur if the Master
Device was reset while sending a Write command to
the MCP47X6, AND then as the Master Device returns
to normal operation and issues a Start condition, while
the MCP47X6 is issuing an Acknowledge. In this case,
if the 2nd Start bit is not sent (and the Stop bit was sent)
the MCP47X6 could initiate a write cycle.
The Stop bit terminates the current I
MCP47X6 waits to detect the next Start condition.
This sequence does not effect any other I
which may be on the bus, as they should disregard this
as an invalid command.
Note:
2
C bus, or is in output mode (from a Read
2
C bus low to acknowledge the data sent by
The potential for this erroneous write
ONLY occurs if the Master Device is reset
while sending a Write command to the
MCP47X6.
© 2011 Microchip Technology Inc.
2
C bus activity. The
2
C devices
2
C