PIC12HV609T-I/MS Microchip Technology, PIC12HV609T-I/MS Datasheet - Page 70

• Manufacturer Part Number: PIC12HV609T-I/MS
• Description: 1.75KB Flash, 64B RAM, 6 I/O, 8MHz Internal Oscillator 8 MSOP 3x3mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12HV609T-I/MS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: FLASH
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Processor Series: PIC12H
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: RS- 232 , USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC12HV609T-I/MSTR

PIC12F609/615/617/12HV609/615
9.5
The comparator interrupt flag can be set whenever
there is a change in the output value of the comparator.
Changes are recognized by means of a mismatch
circuit which consists of two latches and an exclusive-
or gate (see Figure 9-4 and Figure 9-5). One latch is
updated with the comparator output level when the
CMCON0 register is read. This latch retains the value
until the next read of the CMCON0 register or the
occurrence of a Reset. The other latch of the mismatch
circuit is updated on every Q1 system clock. A
mismatch condition will occur when a comparator
output change is clocked through the second latch on
the Q1 clock cycle. At this point the two mismatch
latches have opposite output levels which is detected
by the exclusive-or gate and fed to the interrupt
circuitry. The mismatch condition persists until either
the CMCON0 register is read or the comparator output
returns to the previous state.
The comparator interrupt is set by the mismatch edge
and not the mismatch level. This means that the
interrupt flag can be reset without the additional step of
reading or writing the CMCON0 register to clear the
mismatch registers. When the mismatch registers are
cleared, an interrupt will occur upon the comparator’s
return to the previous state, otherwise no interrupt will
be generated.
Software will need to maintain information about the
status of the comparator output, as read from the
CMCON1 register, to determine the actual change that
has occurred.
The CMIF bit of the PIR1 register is the Comparator
Interrupt flag. This bit must be reset in software by
clearing it to ‘0’. Since it is also possible to write a '1' to
this register, an interrupt can be generated.
The CMIE bit of the PIE1 register and the PEIE and GIE
bits of the INTCON register must all be set to enable
comparator interrupts. If any of these bits are cleared,
the interrupt is not enabled, although the CMIF bit of
the PIR1 register will still be set if an interrupt condition
occurs.
DS41302D-page 70
Note 1: A write operation to the CMCON0 register
2: Comparator
Comparator Interrupt Operation
will also clear the mismatch condition
because all writes include a read
operation at the beginning of the write
cycle.
correctly regardless of the state of
CMOE.
interrupts
will
operate
FIGURE 9-4:
FIGURE 9-5:
Q1
Q3
CIN+
COUT
Set CMIF (edge)
CMIF
Q1
Q3
CIN+
COUT
Set CMIF (edge)
CMIF
Note 1: If a change in the CMCON0 register
cleared by CMCON0 read
2: When a comparator is first enabled, bias
(COUT) should occur when a read
operation is being executed (start of the
Q2 cycle), then the CMIF of the PIR1
register interrupt flag may not get set.
circuitry in the comparator module may
cause
comparator until the bias circuitry is
stable. Allow about 1 s for bias settling
then clear the mismatch condition and
interrupt
comparator interrupts.
T
T
RT
RT
an
COMPARATOR
INTERRUPT TIMING W/O
CMCON0 READ
COMPARATOR
INTERRUPT TIMING WITH
CMCON0 READ
 2010 Microchip Technology Inc.
flags
invalid
reset by software
before
output
reset by software
from
enabling
the