PIC16F721T-I/ML Microchip Technology, PIC16F721T-I/ML Datasheet - Page 160

• Manufacturer Part Number: PIC16F721T-I/ML
• Description: 7 KB FLASH, 256 B SRAM, 18 I/O 20 QFN 4x4mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F721T-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F/LF720/721
REGISTER 17-5:
REGISTER 17-6:
TABLE 17-3:
DS41430A-page 160
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-1
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
INTCON
PIR1
PIE1
SSPBUF
SSPADD
SSPCON
SSPMSK
SSPSTAT
TRISB
Legend:
Note 1:
Name
R/W-1
MSK7
R/W-0
ADD7
2:
(2)
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by SSP module in
I
Maintain these bits clear in I
Accessible only when SSPM<3:0> = 1001.
2
C mode.
TMR1GIE
TMR1GIF
TRISB7
SMP
WCOL
MSK<7:1>: Mask bits
1 = The received address bit n is compared to SSPADD<n> to detect I
0 = The received address bit n is not used to detect I
MSK<0>: Mask bit for I
I
1 = The received address bit ‘0’ is compared to SSPADD<0> to detect I
0 = The received address bit ‘0’ is not used to detect I
All other SSP modes: this bit has no effect.
ADD<7:0>: Address bits
Received address
Bit 7
GIE
2
REGISTERS ASSOCIATED WITH I
C Slave mode, 10-bit Address (SSPM<3:0> = 0111):
(1)
R/W-1
MSK6
R/W-0
ADD6
SSPMSK: SSP MASK REGISTER
SSPADD: SSP I
SSPOV
TRISB6
Synchronous Serial Port Receive Buffer/Transmit Register
CKE
PEIE
ADIF
ADIE
Bit 6
(1)
W = Writable bit
W = Writable bit
‘1’ = Bit is set
‘1’ = Bit is set
R/W-1
MSK5
R/W-0
ADD5
TMR0IE
TRISB5
SSPEN
2
RCIF
RCIE
Bit 5
D/A
C mode.
2
C Slave Mode, 10-bit Address
2
C ADDRESS REGISTER
TRISB4
Bit 4
INTE
TXIF
TXIE
CKP
MSK<7:0>
ADD<7:0>
P
R/W-1
MSK4
R/W-0
ADD4
SSPM3
RABIE
SSPIF
SSPIE
Bit 3
—
S
2
C OPERATION
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-1
MSK3
R/W-0
TMR0IF
CCP1IE
ADD3
CCP1IF
SSPM2
Bit 2
R/W
—
2
C address match
2
C address match
TMR2IE
TMR2IF
SSPM1
Bit 1
INTF
UA
—
R/W-1
MSK2
R/W-0
ADD2
TMR1IF
TMR1IE
SSPM0
RABIF
Bit 0
BF
—
 2010 Microchip Technology Inc.
2
C address match
2
x = Bit is unknown
C address match
x = Bit is unknown
0000 000x
0000 0000
0000 0000
xxxx xxxx
0000 0000
0000 0000
1111 1111
0000 0000
1111 ----
R/W-1
MSK1
POR, BOR
R/W-0
ADD1
Value on
0000 000x
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
1111 1111
0000 0000
1111 ----
R/W-1
Value on
MSK0
all other
R/W-0
ADD0
Resets
bit 0
bit 0