PIC16F721T-I/ML Microchip Technology, PIC16F721T-I/ML Datasheet - Page 32

• Manufacturer Part Number: PIC16F721T-I/ML
• Description: 7 KB FLASH, 256 B SRAM, 18 I/O 20 QFN 4x4mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F721T-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F/LF720/721
3.6
On power-up, the time-out sequence is as follows: first,
PWRT time-out is invoked after POR has expired, then
OST is activated after the PWRT time-out has expired.
The total time-out will vary based on oscillator configu-
ration and PWRTE bit status. For example, in EC mode
with PWRTE bit = 1 (PWRT disabled), there will be no
time-out at all.
depict time-out sequences.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then,
bringing MCLR high will begin execution immediately
(see
to synchronize more than one PIC16F/LF720/721
device operating in parallel.
Table 3-5
registers.
TABLE 3-4:
TABLE 3-5:
FIGURE 3-4:
DS41430A-page 32
EC, INTOSC
Legend: u = unchanged, x = unknown
Oscillator Configuration
POR
0
1
u
u
u
u
Figure
PWRT Time-out
Internal Reset
Time-out Sequence
Internal POR
shows the Reset conditions for some special
3-5). This is useful for testing purposes or
BOR
MCLR
u
0
u
u
u
u
Figure
V
TIME-OUT IN VARIOUS SITUATIONS
RESET BITS AND THEIR SIGNIFICANCE
DD
TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1
3-4,
TO
1
1
0
0
u
1
Figure 3-5
PWRTE = 0
T
PWRT
PD
1
1
u
0
u
0
and
Power-up
Figure 3-6
Power-on Reset
Brown-out Reset
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during Sleep
PWRTE = 1
—
T
PWRT
indicating that a Brown-out has occurred. The BOR
Status bit is a “don’t care” and is not necessarily
predictable if the brown-out circuit is disabled
3.7
The Power Control (PCON) register has two Status bits
to indicate what type of Reset that last occurred.
Bit 0 is BOR (Brown-out Reset). BOR is unknown on
Power-on Reset. It must then be set by the user and
checked on subsequent Resets to see if BOR = 0,
(BOREN<1:0> = 00 in the Configuration Word register).
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a
subsequent Reset, if POR is ‘0’, it will indicate that a
Power-on Reset has occurred (i.e., V
gone too low).
For more information, see
Reset
PWRTE = 0
(BOR)”.
T
PWRT
Power Control (PCON) Register
Brown-out Reset
Condition
T
OST
PWRTE = 1
 2010 Microchip Technology Inc.
—
Section 3.5 “Brown-Out
Wake-up from
DD
Sleep
may have
—