XR16L2450IJ-F Exar Corporation, XR16L2450IJ-F Datasheet - Page 16

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XR16L2450IJ-F

Manufacturer Part Number
XR16L2450IJ-F
Description
2.25 To 5.5V W/ 5V TOLERANT DUART
Manufacturer
Exar Corporation
Datasheet

Specifications of XR16L2450IJ-F

Features
*
Number Of Channels
2, DUART
Fifo's
1 Byte
Protocol
RS232
Voltage - Supply
2.25 V ~ 5.5 V
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
44-LCC (J-Lead)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XR16L2450IJ-F
Manufacturer:
Exar Corporation
Quantity:
10 000
XR16L2450
2.25V TO 5.5V DUART
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
Logic 0 = No parity.
Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format (default).
Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
LCR[5] = logic 0, parity is not forced (default).
LCR[5] = logic 1 and LCR[4] = logic 0, parity bit is forced to a logical 1 for the transmit and receive data.
LCR[5] = logic 1 and LCR[4] = logic 1, parity bit is forced to a logical 0 for the transmit and receive data.
Table 7
BIT-2
LCR B
0
1
1
X
0
0
1
1
for parity selection summary below.
IT
-5 LCR B
BIT-1
0
0
1
1
W
X
0
1
0
1
ORD LENGTH
5,6,7,8
IT
6,7,8
-4 LCR B
T
5
ABLE
BIT-0
0
1
0
1
7: P
0
1
1
1
1
IT
ARITY SELECTION
-3
16
S
Forced parity to space, “0”
TOP BIT LENGTH
Force parity to mark, “1”
W
5 (default)
ORD LENGTH
P
ARITY SELECTION
Even parity
Odd parity
6
7
8
No parity
1 (default)
1-1/2
2
(B
IT TIME
(
S
))
xr
REV. 1.1.1

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