XR16L2450IJ-F Exar Corporation, XR16L2450IJ-F Datasheet - Page 6

• Manufacturer Part Number: XR16L2450IJ-F
• Description: 2.25 To 5.5V W/ 5V TOLERANT DUART
• Manufacturer: Exar Corporation

Specifications of XR16L2450IJ-F

• Features: *
• Number Of Channels: 2, DUART
• Fifo's: 1 Byte
• Protocol: RS232
• Voltage - Supply: 2.25 V ~ 5.5 V
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XR16L2450
2.25V TO 5.5V DUART
The XR16L2450 (L2450) integrates the functions of 2 16C450 Universal Asynchrounous Receiver and
Transmitter (UART). Each UART is independently controlled having its own set of device configuration
registers. The L2450 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-
to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for
converting the serial data stream into parallel data that is required with digital data systems. Synchronization
for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data
character (character orientated protocol). Data integrity is ensured by attaching a parity bit to the data
character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to
provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip.
The L2450 represents such an integration with greatly enhanced features. The L2450 is fabricated with an
advanced CMOS process. The L2450 is capable of operation up to 1.5 Mbps with a 24 MHz clock. With a
crystal or external clock input of 14.7456 MHz the user can select data rates up to 921.6 Kbps.
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The L2450 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C450 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# signals. Both UART channels share
the same data bus for host operations. The data bus interconnections are shown in
.
The L2450 can accept up to 5V inputs even when operating at 3.3V or 2.5V. But note that if the L2450 is
operating at 2.5V, its V
transceiver that is operating at 5V.
The RESET input resets the internal registers and the serial interface outputs in both channels to their default
state (see
in the device.
1.0 PRODUCT DESCRIPTION
2.0 FUNCTIONAL DESCRIPTIONS
2.1
2.2
2.3
CPU Interface
5-Volt Tolerant Inputs
Device Reset
Table
F
IGURE
UART_RESET
UART_CSA#
UART_CSB#
8). An active high pulse of at least 40 ns duration will be required to activate the reset function
UART_INTA
UART_INTB
3.
IOW#
IOR#
A0
A1
A2
D0
D1
D2
D3
D4
D5
D6
D7
OH
XR16L2450 D
may not be high enough to meet the requirements of the V
ATA
B
US
I
NTERCONNECTIONS
6
IOR#
IOW#
CSA#
CSB#
RESET
D0
D1
D2
D3
D4
D5
D6
D7
INTA
INTB
A0
A1
A2
Channel A
Channel B
UART
UART
DTRA#
DSRA#
RTSA#
CTSA#
DTRB#
DSRB#
OP2A#
RTSB#
CTSB#
OP2B#
CDA#
CDB#
GND
RIA#
RIB#
VCC
TXA
RXA
TXB
RXB
VCC
RS-232 Serial Interface
RS-232 Serial Interface
Figure
IH
of a CPU or a serial
3.
xr
REV. 1.1.1