XR16L2450IJ-F Exar Corporation, XR16L2450IJ-F Datasheet - Page 9

• Manufacturer Part Number: XR16L2450IJ-F
• Description: 2.25 To 5.5V W/ 5V TOLERANT DUART
• Manufacturer: Exar Corporation

Specifications of XR16L2450IJ-F

• Features: *
• Number Of Channels: 2, DUART
• Fifo's: 1 Byte
• Protocol: RS232
• Voltage - Supply: 2.25 V ~ 5.5 V
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

xr
REV. 1.1.1
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 1 byte FIFO or Transmit
Holding Register (THR). TSR shifts out every data bit with the 16X internal clock. A bit time is 16 clock periods.
The transmitter sends the start-bit followed by the number of data bits, inserts the proper parity-bit if enabled,
and adds the stop-bit(s). The status of the FIFO and TSR are reported in the Line Status Register (LSR bit-5
and bit-6).
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
2.10
2.10.1
O
UTPUT
MCR Bit-7=0
153.6k
230.4k
460.8k
921.6k
19.2k
38.4k
76.8k
2400
4800
9600
Transmitter
400
Data Rate
Transmit Holding Register (THR) - Write Only
T
F
ABLE
IGURE
16X Clock
3: T
Clock (Decimal)
D
5. T
IVISOR FOR
YPICAL DATA RATES WITH A
Data
Byte
RANSMITTER
2304
384
192
96
48
24
12
6
4
2
1
16x
Transmit Shift Register (TSR)
O
D
PERATION
IVISOR FOR
Clock (HEX)
Transmit
Register
Holding
(THR)
900
180
C0
0C
60
30
18
06
04
02
01
16x
14.7456 MH
9
DLM P
V
ALUE
THR Interrupt (ISR bit-1)
Z CRYSTAL OR EXTERNAL CLOCK
Enabled by IER bit-1
09
01
00
00
00
00
00
00
00
00
00
ROGRAM
(HEX)
M
S
B
DLL P
V
ALUE
TXNOFIFO1
L
S
B
C0
0C
00
80
60
30
18
06
04
02
01
ROGRAM
(HEX)
2.25V TO 5.5V DUART
D
XR16L2450
E
ATA
RROR
0
0
0
0
0
0
0
0
0
0
0
R
ATE
(%)