ISP1504ABS,118 NXP Semiconductors, ISP1504ABS,118 Datasheet - Page 55

• Manufacturer Part Number: ISP1504ABS,118
• Description: RF Transceiver USB ULPI TRANSCEIVER
• Manufacturer: NXP Semiconductors

Specifications of ISP1504ABS,118

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Operating Supply Voltage (typ): Not RequiredV
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): Not RequiredV
• Operating Supply Voltage (min): Not RequiredV
• Pin Count: 32
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Supply Voltage: 1.65 V to 3.6 V
• Mounting Style: SMD/SMT
• Package / Case: HVQFN-32
• Lead Free Status / RoHS Status: Compliant
• Other names: 935278308118 ISP1504ABS-T

NXP Semiconductors
Table 38.
Table 39.
Table 40.
Table 41.
ISP1504A_ISP1504C_3
Product data sheet
Bit
7 to 5
4
3
2
1
0
Bit
Symbol
Reset
Access
Bit
7 to 2
1
0
Bit
7 to 0
Symbol
-
ID_GND_L
SESS_END_L
SESS_VALID_L
VBUS_VALID_L
HOST_DISCON_L
Symbol
SCRATCH[7:0]
Symbol
-
LINESTATE1
LINESTATE0
USB Interrupt Latch register (address R = 14h) bit description
Debug register (address R = 15h) bit allocation
Debug register (address R = 15h) bit description
Scratch register (address R = 16h to 18h, W = 16h, S = 17h, C = 18h) bit description
10.1.10 Scratch register
10.1.11 Reserved
10.1.12 Access extended register set
10.1.9 Debug register
R
7
0
The bit allocation of the Debug register is given in
current value of signals useful for debugging.
This is an empty register for testing purposes; see
Registers 19h to 2Eh are not implemented. Operating on these addresses will have no
effect on the PHY.
Address 2Fh does not contain register data. Instead it links to the extended register set.
The immediate register set maps to the lower end of the extended register set.
Access
R/W/S/C
Description
reserved
Line State 1: Contains the current value of LINESTATE 1.
Line State 0: Contains the current value of LINESTATE 0.
Description
reserved
ID Ground Latch: Automatically set when an unmasked event occurs on ID_GND. Cleared
when this register is read.
Session End Latch: Automatically set when an unmasked event occurs on SESS_END.
Cleared when this register is read.
Session Valid Latch: Automatically set when an unmasked event occurs on SESS_VLD.
Cleared when this register is read.
V
Cleared when this register is read.
Host Disconnect Latch: Automatically set when an unmasked event occurs on
HOST_DISCON. Cleared when this register is read.
BUS
R
6
0
Valid Latch: Automatically set when an unmasked event occurs on A_VBUS_VLD.
Value
00h
R
5
0
reserved
Description
Scratch: This is an empty register byte for testing purposes. Software
can read, write, set and clear this register. The functionality of PHY will
not be affected.
Rev. 03 — 7 April 2008
R
4
0
R
3
0
ISP1504A; ISP1504C
Table
Table
39. This register indicates the
41.
ULPI HS USB OTG transceiver
R
2
0
STATE1
LINE
R
1
0
© NXP B.V. 2008. All rights reserved.
STATE0
LINE
R
0
0
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