ISP1505ABS STEricsson, ISP1505ABS Datasheet - Page 14

• Manufacturer Part Number: ISP1505ABS
• Manufacturer: STEricsson

Specifications of ISP1505ABS

• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
8. Modes of operation
ISP1505A_ISP1505C_3
Product data sheet
8.1.1 Synchronous mode
8.1 ULPI modes
The ISP1505 ULPI bus can be programmed to operate in four modes. Each mode
reconfigures the signals on the data bus as described in the following subsections. Setting
more than one mode will lead to undefined behavior.
This is default mode. At power-up, and when CLOCK is stable, the ISP1505 will enter
synchronous mode. The link must synchronize all ULPI signals to CLOCK, meeting the
set-up and hold times as defined in
synchronous mode is given in
This mode is used by the link to perform the following tasks:
For more information on various synchronous mode protocols, see
Table 3.
Signal
name
CLOCK
DATA[7:0] I/O
•
•
•
•
High-speed detection handshake (chirp)
Transmit and receive USB packets
Read and write to registers
Receive USB status updates (RXCMDs)
ULPI signal description
Direction on
ISP1505
O
Rev. 03 — 26 August 2008
Signal description
60 MHz interface clock. If a crystal is attached or a clock is driven into
the XTAL1 pin, the ISP1505 will drive a 60 MHz output clock.
8-bit data bus. In synchronous mode, the link drives DATA[7:0] to LOW
by default. The link initiates transfers by sending a nonzero data pattern
called TXCMD (transmit command). In synchronous mode, the direction
of DATA[7:0] is controlled by DIR. Contents of DATA[7:0] lines must be
ignored for exactly one clock cycle whenever DIR changes value. This is
called the turnaround cycle.
Data lines have fixed direction and different meaning in low-power and
serial modes.
Table
Section
3.
ULPI HS USB host and peripheral transceiver
15. A description of the ULPI pin behavior in
ISP1505A; ISP1505C
Section
© NXP B.V. 2008. All rights reserved.
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