ISP1505ABS STEricsson, ISP1505ABS Datasheet - Page 49

• Manufacturer Part Number: ISP1505ABS
• Manufacturer: STEricsson

Specifications of ISP1505ABS

• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 30.
Table 31.
Table 32.
Table 33.
ISP1505A_ISP1505C_3
Product data sheet
Bit
7 to 4
3
2
1
0
Bit
Symbol
Reset
Access
Bit
7 to 4
3
2
1
0
Bit
Symbol
Reset
Access
Symbol
-
SESS_END_R
SESS_VALID_R
VBUS_VALID_R
HOST_DISCON_R
Symbol
-
SESS_END_F
SESS_VALID_F
VBUS_VALID_F
HOST_DISCON_F Host Disconnect Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on
USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh, C = 0Fh) bit
description
USB Interrupt Enable Falling Edge register (address R = 10h to 12h, W = 10h, S = 11h, C = 12h) bit
allocation
USB Interrupt Enable Falling Edge register (address R = 10h to 12h, W = 10h, S = 11h, C = 12h) bit
description
USB Interrupt Status register (address R = 13h) bit allocation
10.1.6 USB Interrupt Enable Falling Edge register
10.1.7 USB Interrupt Status register
R/W/S/C
X
R
7
0
7
The bits in this register enable interrupts and RXCMDs to be sent when the corresponding
bits in the USB Interrupt Status register change from logic 1 to logic 0. By default, all
transitions are enabled. See
This register (see
R/W/S/C
Description
reserved
Session End Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on
SESS_END.
Session Valid Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on
SESS_VLD.
V
A_VBUS_VLD.
Host Disconnect Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on
HOST_DISCON.
Description
reserved
Session End Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on
SESS_END.
Session Valid Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on
SESS_VLD.
V
A_VBUS_VLD.
HOST_DISCON.
BUS
BUS
R
X
6
0
6
Valid Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on
Valid Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on
reserved
reserved
R/W/S/C
Table
X
R
5
0
5
Rev. 03 — 26 August 2008
33) indicates the current value of the interrupt source signal.
Table
R/W/S/C
R
4
1
4
0
31.
ULPI HS USB host and peripheral transceiver
R/W/S/C
SESS_
END_F
SESS_
END
R
3
1
3
0
ISP1505A; ISP1505C
VALID_F
R/W/S/C
SESS_
SESS_
VALID
R
2
1
2
0
VALID_F
R/W/S/C
VBUS_
VBUS_
VALID
R
1
1
1
0
© NXP B.V. 2008. All rights reserved.
DISCON_F
R/W/S/C
DISCON
HOST_
HOST_
R
0
1
0
0
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