SAF7118EHV1 NXP Semiconductors, SAF7118EHV1 Datasheet - Page 55

• Manufacturer Part Number: SAF7118EHV1
• Manufacturer: NXP Semiconductors

Specifications of SAF7118EHV1

• Screening Level: Industrial
• Package Type: HBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SAF7118_4
Product data sheet
8.4.3.1 Line FIFO buffer (subaddresses 91h, B4h and C1h, E4h)
8.4.3 Vertical scaling
Luminance and chrominance scale increments (XSCY[12:0] A9h[4:0] A8h[7:0] and
XSCC[12:0] ADh[4:0] ACh[7:0]) are defined independently, but must be set in a 2 : 1
relationship in the actual data path implementation. The phase offsets XPHY[7:0]
AAh[7:0] and XPHC[7:0] AEh[7:0] can be used to shift the sample phases slightly.
XPHY[7:0] and XPHC[7:0] covers the phase offset range 7.999T to
offsets should also be programmed in a 2 : 1 ratio.
The underlying phase controlling DTO has a 13-bit resolution.
According the equations:
the VPD covers the scale range from 0.125 to zoom 3.5. VPD acts equivalent to a
polyphase filter with 64 possible phases. In combination with the prescaler, it is possible to
get very accurate samples from a highly anti-aliased integer downscaled input picture.
The vertical scaler of the SAF7118 consists of a line FIFO buffer for line repetition and the
vertical scaler block, which implements the vertical scaling on the input data stream in
2 different operational modes from theoretical zoom by 64 down to icon size
vertical scaler is located between the BCS and horizontal fine scaler, so that the BCS can
be used to compensate the DC gain amplification of the ACM mode (see
as the internal RAMs are only 8-bit wide.
The line FIFO buffer is a dual ported RAM structure for 768 pixels, with asynchronous
write and read access. The line buffer can be used for various functions, but not all
functions may be available simultaneously.
The line buffer can buffer a complete unscaled active video line or more than one shorter
lines (only for non-mirror mode), for selective repetition for vertical zoom-up.
For zooming up 240 lines to 288 lines e.g., every fourth line is requested (read) twice from
the vertical scaling circuitry for calculation.
For conversion of a 4 : 2 : 0 or 4 : 1 : 0 input sampling scheme (MPEG, video phone,
Indeo YUV-9) to ITU like sampling scheme 4 : 2 : 2, the chrominance line buffer is read
twice or four times, before being refilled again by the source. It has to be preserved by
means of the input acquisition window definition, so that the processing starts with a line
containing luminance and chrominance information for 4 : 2 : 0 and 4 : 1 : 0 input. The bits
FSC[2:1] 91h[2:1] define the distance between the Y/C lines. In the event of 4 : 2 : 2 and
4 : 1 : 1 FSC2 and FSC1 have to be set to ‘00’.
The line buffer can also be used for mirroring, i.e. for flipping the image left to right, for the
vanity picture in video phone applications (bit YMIR[B4h[4]]). In mirror mode only one
active prescaled line can be held in the FIFO at a time.
The line buffer can be utilized as an excessive pipeline buffer for discontinuous and
variable rate transfer conditions at the expansion port or image port.
XSCY[12:0]
=
1024
-------------------------- -
XPSC[5:0]
Npix_in
Rev. 04 — 4 July 2008
Multistandard video decoder with adaptive comb filter
--------------------- -
Npix_out
1
and
XSCC[12:0]
=
XSCY[12:0]
---------------------------- -
1
32
2
SAF7118
T. The phase
© NXP B.V. 2008. All rights reserved.
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8.4.3.2)
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