SAF7118EHV1 NXP Semiconductors, SAF7118EHV1 Datasheet - Page 79

• Manufacturer Part Number: SAF7118EHV1
• Manufacturer: NXP Semiconductors

Specifications of SAF7118EHV1

• Screening Level: Industrial
• Package Type: HBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SAF7118_4
Product data sheet
Fig 42. Output timing I port for serial 8-bit data at start of a line (ICODE = 1)
IPD [ 7:0 ]
IGPH
ICLK
IDQ
00
9.8.1 I port output timing
9.8.2 X port input timing
9.8 Basic input and output timing diagrams I port and X port
FF
Table 34.
[1]
The following diagrams illustrate the output timing via the I port. IGPH and IGPV are
logic 1 active gate signals. If reference pulses are programmed, these pulses are
generated on the rising edge of the logic 1 active gates. Valid data is accompanied by the
output data qualifier on pin IDQ. In addition invalid cycles are marked with output code
00h.
The IDQ output pin may be defined to be a gated clock output signal
(ICLK AND internal IDQ).
At the X port the input timing requirements are the same as those for the I port output. But
different to those below:
Remark: All timings illustrated in
output stream (no handshake with the external hardware).
Symbol Pin
HPD7 to
HPD0
•
•
•
00
Pin numbers for QFP160 in parenthesis.
It is not necessary to mark invalid cycles with a 00h code
No constraints on the input qualifier (can be a random pattern)
XCLK may be a gated clock (XCLK AND external XDQ)
00
G13, F14,
F13, E14,
E12, E13,
E11 and D14
(103, 105,
107 and 109
to 113)
Signals dedicated to the host port
[1]
SAV
00
I/O
I/O
Rev. 04 — 4 July 2008
C
B
Description
16-bit extension for digital I/O (chrominance
component)
Y
Multistandard video decoder with adaptive comb filter
Figure 42
C
R
Y
to
Figure 48
00
are given for an uninterrupted
C
B
Y
Bit
IPE[1:0] 87h[1:0],
ITRI[8Fh[6]] and
I8_16[93h[6]]
SAF7118
C
© NXP B.V. 2008. All rights reserved.
R
Y
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