MT49H16M18CBM-25 Micron Technology Inc, MT49H16M18CBM-25 Datasheet
MT49H16M18CBM-25
Specifications of MT49H16M18CBM-25
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MT49H16M18CBM-25 Summary of contents
Page 1
... 1.5V or 1.8V V EXT DD • On-die termination (ODT PDF: 09005aef80a41b59/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_D1.fm - Rev. P 1/11 EN Products and specifications discussed herein are subject to change by Micron without notice. 288Mb: x18 2.5V V ® II Options • Clock cycle timing – 1.875ns @ – 2.5ns @ – ...
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... Figure 1: 288Mb RLDRAM II SIO Part Numbers MT49H Configuration 16 Meg x 18 BGA Part Marking Decoder Due to space limitations, BGA-packaged components have an abbreviated part marking that is different from the part number. Micron’s BGA Part Marking Decoder is available on Micron’s Web site at www.micron.com. ...
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... Disabling the JTAG Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Test Access Port (TAP .64 TAP Controller .65 Performing a TAP RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 TAP Registers .67 TAP Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 PDF: 09005aef80a41b59/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIOTOC.fm - Rev. P 1/11 EN 288Mb: x18 2. 1.8V V EXT Micron Technology, Inc., reserves the right to change products or specifications without notice HSTL, SIO, RLDRAM II ...
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... List of Figures Figure 1: 288Mb RLDRAM II SIO Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Figure 2: State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Figure 3: Functional Block Diagram – 64 Meg Figure 4: Functional Block Diagram – 32 Meg x 18 Figure 5: 144-Ball µBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Figure 6: Clock Input . Figure 7: Nominal AS/ CS/ DS and Figure 8: Example Temperature Test Point Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Figure 9: Mode Register Set ...
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... Identification Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Table 27: Scan Register Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Table 28: Instruction Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Table 29: Boundary Scan (Exit) Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 PDF: 09005aef80a41b59/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIOLOT.fm - Rev. P 1/11 EN 288Mb: x18 2. 1.8V V EXT Micron Technology, Inc., reserves the right to change products or specifications without notice HSTL, SIO, RLDRAM II DD List of Tables ...
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... Read and write accesses to the RLDRAM are burst-oriented. The burst length (BL) is programmable from setting the mode register. The device is supplied with 2.5V and 1.8V for the core and 1.5V or 1.8V for the output drivers ...
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... Figure 2: State Diagram WRITE MRS PDF: 09005aef80a41b59/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_D2.fm - Rev. P 1/11 EN 288Mb: x18 2. 1.8V V EXT Initialization sequence DSEL/NOP Automatic sequence Command sequence Micron Technology, Inc., reserves the right to change products or specifications without notice HSTL, SIO, RLDRAM II DD General Description READ AREF ...
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Functional Block Diagrams Figure 3: 16 Meg x 18 Functional Block Diagram ZQ ODT control CK CK# Control CS# logic REF# WE# Refresh 13 counter Mode register Row- address MUX A0–A19 Address 23 BA0–BA2 register 3 1 ...
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... This may be optionally connected to GND function. This signal is internally connected and has parasitic characteristics of a clock input signal. This may be optionally connected to GND. PDF: 09005aef80a41b59/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_D2.fm - Rev. P 1/11 EN 288Mb: x18 2.5V V EXT Ball Assignments and Descriptions ...
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... Output data clocks: QKx and QKx# are opposite polarity, output data clocks. They are free- running, and during READs are edge-aligned with data output from the RLDRAM. QKx# is ideally 180 degrees out of phase with QKx. QK0 and QK0# are aligned with Q0–Q8 and QK1 and QK1# are aligned with Q9– ...
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... Solder ball material: Eutectic (62% Sn, 36% Pb, 2% Ag) or SAC305 (96.5% Sn, 3% Ag, 0.5% Cu). Dimensions apply solder balls post-reflow on Ø0.39 SMD ball pads. 17 CTR 1 TYP Notes: 1. All dimensions are in millimeters. PDF: 09005aef80a41b59/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_D2.fm - Rev. P 1/11 EN 288Mb: x18 2.5V V 10º TYP 0.73 ±0.1 Ball 18.5 ± ...
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... Measurement is taken during continuous READ Operating burst Cyclic bank access; Half of read current address bits change every 4 clock cycles; example Measurement is taken during continuous READ PDF: 09005aef80a41b59/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_D2.fm - Rev. P 1/11 EN 288Mb: x18 2. Symbol I (V SB1 SB1 EXT ...
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... Measurement is taken during continuous READ Operating burst Cyclic bank access; Half of read current address bits change every 4 clock example cycles; Measurement is taken during continuous READ Notes ≤ PDF: 09005aef80a41b59/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_D2.fm - Rev. P 1/11 EN 288Mb: x18 2.5V V Symbol SB1 SB1 EXT SB2 ...
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... AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 2 V/ns in the range between V V IH(AC) PDF: 09005aef80a41b59/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_D2.fm - Rev. P 1/11 EN 288Mb: x18 2.5V V conditions: DD ≤ V MAX. ...
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... V DDQ 4. Typically the value of V expected to track variations Peak-to-peak AC noise REF level of the same. Peak-to-peak noise (non-common mode the DC value. Thus, from V ±2% V itor. PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2. Conditions Symbol – V EXT – – ...
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... V REF from each data input signal to the nearest 125–185Ω at 95° and I are defined as absolute values and are measured flows into the device. OL and V , refer to the RLDRAM II HSPICE or IBIS driver models ≤ +95°C; +1.7V ≤ Symbol (GND). SS and V ...
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... DDQ MIN IN(DC) Notes and CK# must cross within this region and CK# must meet at least V 3. Minimum peak-to-peak swing violation to tri-state CK and CK# after the part is initialized. PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2.5V V Symbol V IN(DC) V ID(DC) V ID(AC) V IX(AC) (GND). SS ...
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... The hold values in Table 10 and Table 11 are also valid for rising signals (with respect to V IL[DC] Note: The above descriptions also pertain to data setup and hold derating when CK/CK# are replaced with DK/DK#. PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2. specifications when the slew rate of any of these input signals is less than t t AS/ ...
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... PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2. AS IH(AC Min to CK/CK# AH/ CH CK/CK# Crossing Crossing to V CK, CK# Differential Slew Rate: 2.0 V/ns –100 –100 –100 –100 – ...
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... PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2.5V V EXT Electrical Specifications – AC and Min to DH CK/CK# IH(AC) CK/CK# Crossing Crossing to V DK, DK# Differential Slew Rate: 2.0 V/ns –100 0 – ...
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... Capacitance – µBGA Description Address/control input capacitance Input/output capacitance (D, Q, DM, and QK/QK#) Clock capacitance (CK/CK#, and DK/DK#) JTAG pins Notes: 1. Capacitance is not tested on ZQ pin. 2. JTAG pins are tested at 50 MHz. PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2. and AH/ CH/ DH Slew Rate ...
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... QHP MIN Half-clock period t ( QKH, t QKL edge to clock CKQK –0.2 edge skew t QKQ0, –0.12 QK edge to t QKQ1 output data edge PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2.5V V -18 -25E -25 Max Min Max Min 5.7 2.5 5.7 2 100 –150 150 – ...
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... Data valid DVW QHP - t window ( QKQx [MAX QKQx [MIN]|) Refresh t REFI – Average periodic refresh interval PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2.5V V -18 -25E -25 Max Min Max Min 0.22 –0.3 0.3 –0.3 0.22 –0.3 0.3 –0 – QHP - – ...
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... QKQ takes into account the skew between any QKx and any improve efficiency, eight AREF commands (one for each bank) can be posted to the RLDRAM on consecutive cycles at periodic intervals of 3.90µs. PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2.5V V EXT Electrical Specifications – ...
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... Table 14. For designs that are expected to last several years and require the flexi- bility to use several DRAM die shrinks, consider using final target theta values (rather than existing values) to account for increased thermal impedances from the die size reduction. The RLDRAM device’ ...
Page 26
... Thermal impedance data is based on a number of samples from multiple lots and should be viewed as a typical number. Figure 8: Example Temperature Test Point Location Test point PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2.5V V Temperature and Thermal Impedance θ JA (°C/W) Airflow = 1m/s 41.2 29 ...
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... Description of Commands Command DSEL/NOP The NOP command is used to perform a no operation to the RLDRAM, which essentially deselects the chip. Use the NOP command to prevent unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. Output values depend on command history. ...
Page 28
... After issuing a valid MRS command, command can be issued to the RLDRAM. This statement does not apply to the consecu- tive MRS commands needed for internal logic reset during the initialization routine. The MRS command can only be issued when all banks are idle and no other operation is in progress ...
Page 29
... Internal 50Ω 5 (default Notes: 1. A10–A17 must be set to zero; A18–An = “Don’t Care.” not used in MRS not available. 4. DLL RESET turns the DLL off. 5. ±30% temperature variation. PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2.5V V A17 A10 17–10 ...
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... Burst Length (BL) Burst length is defined by M3 and M4 of the mode register. Read and write accesses to the RLDRAM are burst-oriented, with the burst length being programmable Figure 11 on page 34 illustrates the different burst lengths with respect to a READ command. Changes in the burst length affect the width of the address bus (see for details) ...
Page 31
... DRAM. In multiplexed address mode, the address can be provided to the RLDRAM in two parts that are latched into the memory with two consecutive rising clock edges. This provides the advantage of only needing a maximum of 11 address balls to control the RLDRAM, reducing the number of signals on the controller side ...
Page 32
... ODT. The ODT function is dynamically switched off when a Q begins to drive after a READ command is issued. Similarly, ODT is designed to switch on at the Qs after the RLDRAM has issued the last piece of data. The D and DM pins will always be terminated. See section entitled "Operations" on page 40 for relevant timing diagrams. ...
Page 33
... Table 20: On-Die Termination DC Parameters Description Termination voltage On-die termination Notes: 1. All voltages referenced The R Figure 12: On-Die Termination-Equivalent Circuit D PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2.5V V Symbol (GND expected to be set equal to V REF value is measured at 95° Receiver 36 , 1.8V V ...
Page 34
... WRITE command. During WRITE commands, data will be registered at both edges of DK according to the programmed burst length (BL). The RLDRAM operates with a WRITE latency (WL) that is one cycle longer than the programmed READ latency (RL + 1), with the first valid data registered at the first rising DK edge WL cycles after the WRITE command ...
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... READ Command CK# CK CS# WE# REF# ADDRESS BANK ADDRESS PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2. QKQ0 is referenced to Q0–Q8). t QKQx is derived at each QKx clock edge and is not cumulative over time. ID(DC QKQ [MAX QKQ [MIN]|). See Figure 27 on page 50 for illustration. ...
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... RLDRAM requires 64K cycles at an average periodic interval of 0.49µs MAX (actual periodic refresh interval is 32ms/8K rows/8 banks = 0.488µs). To improve effi- ciency, eight AREF commands (one for each bank) can be posted to the RLDRAM at peri- odic intervals of 3.9µs (32ms/8K rows = 3.90µs). Figure 28 on page 51 illustrates an example of a refresh sequence ...
Page 37
... Apply NOP conditions to command pins. Ensuring CK/CK# meet V t MRSC does not need to be met between these consecutive before V DDQ is at the same level CK/CK# can not be met prior to being applied to the RLDRAM, placing a ID(DC 1. HSTL, SIO, RLDRAM II EXT and start clock as soon as the supply volt- ...
Page 38
... The sequence of the eight AUTO REFRESH commands (with respect to the 1,024 NOP com- mands) does not matter required for any operation, tRC must be met between an AUTO REFRESH command and a subsequent VALID command to the same bank. PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2. ...
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... The sequence of the eight AUTO REFRESH commands (with respect to the 1024 NOP com- mands) does not matter required for any operation, AUTO REFRESH command and a subsequent VALID command to the same bank. PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2. and V ramp ...
Page 40
... CKDK (NOM) DK CKDK (MIN DK CKDK (MAX DK Notes data-in for address n; subsequent elements of burst are applied following DI an PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2. NOP NOP CKDK t CKDK HSTL, SIO, RLDRAM II EXT DD T6 T6n T4 T5 T5n NOP NOP NOP ...
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... Three subsequent elements of the burst are applied following DI for each bank Each WRITE command may be to any bank; if the second WRITE is to the same bank must be met. 5. Nominal conditions are assumed for specifications not defined. PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2. WRITE NOP WRITE ...
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... DM Notes data-in for bank a and address data-out from bank b and address n. 3. Three subsequent elements of each burst follow DI an and DO bn Nominal conditions are assumed for specifications not defined. PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2. 1.8V V EXT NOP NOP ...
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... WRITE NOP Bank a, ADDRESS Add n DK Notes data-in from address n. 2. Subsequent elements of burst are provided on following clock edges Nominal conditions are assumed for specifications not defined. PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2. NOP NOP NOP 1. HSTL, SIO, RLDRAM II ...
Page 44
... DM t CKQK (MIN) QK# QK QVLD Q t CKQK (MAX) QK# QK QVLD Q Notes data-out from address n. 2. Three subsequent elements of the burst are applied following Nominal conditions are assumed for specifications not defined. PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2. NOP NOP ...
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... Bank address can be to any bank, but the subsequent READ can only be to the same bank has been met. 6. Data from the READ commands to banks c and d will appear on subsequent clock cycles that are not shown. PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2. READ ...
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... Notes data-out from bank x and address data-in for bank x and address n. 3. Three subsequent elements of each burst follow each DI xn and DO xn Nominal conditions are assumed for specifications not defined. PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2. T4n NOP NOP ...
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... QKQ0 is referenced to Q0–Q8 QKQ1 is referenced to Q9–Q17 QKQ takes into account the skew between any QKx and any Q. PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2.5V V QK0# QK0 t QHP 1 t QKQ0 (MAX QKQ0 (MAX QKQ0 (MAX QKQ0 (MIN QKQ0 (MIN ...
Page 48
... Figure 28: AUTO REFRESH Cycle COMMAND ADDRESS BANK DK, DK# DM Notes: 1. AREFx = AUTO REFRESH command to bank x. 2. ACx = any command to bank x; ACy = any command to bank y. 3. BAx = bank address to bank x; BAy = bank address to bank y. PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2. CK ...
Page 49
... Q Q ODT QK# QK QVLD Q Q ODT Notes data out followed by the remaining bits of the burst. 3. Nominal conditions are assumed for specifications not defined. PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2. NOP NOP NOP DO Q ODT on Q ODT on Q ODT ...
Page 50
... Q ODT on Notes data-out from bank a and address data-in for bank b and address Three subsequent elements of each burst appear after each DO an and DI bn. 4. Nominal conditions are assumed for specifications not defined. PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2. READ NOP ...
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... WE# REF# ADDRESS Ax Ay BANK BA ADDRESS Notes: 1. The minimum setup and hold times of the two address parts are defined PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2. 1.8V V EXT WRITE MRS Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 52
... Address A5 must be set HIGH. This and the following step set the desired mode register once the RLDRAM is in multiplexed address mode. 5. Any command or address. 6. The above sequence must be followed in order to power up the RLDRAM in the multiplexed address mode. 7. DLL must be reset and CK# must separated at all times to prevent bogus commands from being issued. ...
Page 53
... DLL RESET turns the DLL off. 6. BA0–BA2 are “Don’t Care.” 7. Addresses A0, A3, A4, A5, A8, and A9 must be set as shown in order to activate the mode register in the multiplexed address mode. PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2.5V V A18 . . . A10 A9 ...
Page 54
... Address Mapping in Multiplexed Address Mode Note 1 applies to the entire table Data Burst Width Length Ball A0 x18 Notes “Don’t Care.” address is reserved for A20 expansion in multiplexed mode address is reserved for A21 expansion in multiplexed mode. PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2. ...
Page 55
... Configuration Tables in Multiplexed Address Mode In multiplexed address mode, the read and write latencies are increased by one clock cycle. However, the RLDRAM cycle time remains the same as when in non-multiplexed address mode. Table 22: Cycle Time and READ/WRITE Latency Configuration Table in Multiplexed Mode Notes 1–2 apply to the entire table ...
Page 56
... data-in for bank data-in for bank b. 3. Three subsequent elements of the burst are applied following DI for each bank. 4. Each WRITE command may be to any bank; if the second WRITE is to the same bank, must be met. PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2. ...
Page 57
... One subsequent element of each burst follows DI a and Nominal conditions are assumed for specifications not defined. 6. Bank address can be to any bank, but the subsequent READ can only be to the same bank has been met. PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2. 1.8V V EXT ...
Page 58
... Bank address can be to any bank, but the subsequent READ can only be to the same bank has been met. 7. Data from the READ commands to banks b through bank d will appear on subsequent clock cycles (not shown). PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2. NOP ...
Page 59
... Three subsequent elements of the burst which appear following DI bn are not all shown. 7. Bank address can be to any bank, but the WRITE command can only be to the same bank has been met. PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2. WRITE ...
Page 60
... M8 needs to be set to 0 until the JTAG testing of the pin is complete. Note that upon power up, the default state of MRS bit M8 is low. If the RLDRAM boundary scan register used upon power up and prior to the initialization of the RLDRAM device imperative that the CK and CK# pins meet ...
Page 61
... The pause-DR state is entered when the shifting of data through the test registers needs to be suspended. When shifting is to reconvene, the controller enters the exit2-DR state and then can re-enter the shift-DR state. PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2. 1.8V V EXT IEEE 1149 ...
Page 62
... Figure 40: TAP Controller State Diagram Test-logic 1 Run-test/ 0 Figure 41: TAP Controller Block Diagram TDI TCK TMS Notes 112 for all configurations. PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2.5V V IEEE 1149.1 Serial Boundary Scan (JTAG) reset Select Idle DR-scan 0 1 Capture-DR 0 ...
Page 63
... Table 29 on page 71 shows the order in which the bits are connected. Each bit corre- sponds to one of the balls on the RLDRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the capture-DR state when the IDCODE command is loaded in the instruction register ...
Page 64
... The user must be aware that the TAP controller clock can only operate at a frequency MHz, while the RLDRAM clock operates significantly faster. Because there is a large difference between the clock frequencies possible that during the capture-DR state, an input or output will undergo a transition ...
Page 65
... STATE TDO T10 T11 T12 TCK TMS TDI TAP Select-DR- CONTROLLER Exit 2-IR Update-IR STATE TDO PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2.5V V IEEE 1149.1 Serial Boundary Scan (JTAG Select-DR- Select-IR- Capture-IR SCAN SCAN T13 T14 T15 Capture-DR Shift-DR ...
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... TCK HIGH to TDI invalid Setup times TMS setup Capture setup Hold times TMS hold Capture hold t Notes and ary scan register. PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN 288Mb: x18 2.5V V IEEE 1149.1 Serial Boundary Scan (JTAG (TCK) t THTL t t THTH TLTH t MVTH t THMX ...
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... I/O, 1 for separate I for RLDRAM II 00000101100 Allows unique identification of RLDRAM vendor 1 Indicates the presence register Micron Technology, Inc., reserves the right to change products or specifications without notice 1.8V V ...
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... TDO; This operation does not affect RLDRAM operations. Loads the ID register with the vendor ID code and places the register between TDI and TDO; This operation does not affect RLDRAM operations. Captures I/O ring contents; Places the boundary scan register between TDI and TDO. Selects the bypass register to be connected between TDI and TDO ...
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... Customer Comment Line: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. RLDRAM is a registered trademark of Qimonda AG in various coun- tries, and is used by Micron Technology, Inc. under license from Qimonda.All other trademarks are the property of their respective owners. ...