MT49H16M18CBM-25 Micron Technology Inc, MT49H16M18CBM-25 Datasheet - Page 37

• Manufacturer Part Number: MT49H16M18CBM-25
• Manufacturer: Micron Technology Inc
• Type: RLDRAMr

Specifications of MT49H16M18CBM-25

• Organization: 16Mx18
• Density: 288Mb
• Address Bus: 23b
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: uBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 779mA
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Operations
INITIALIZATION
PDF: 09005aef815b2df8/Source: 09005aef811ba111
288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN
Notes:
1. It is possible to apply V
2. If V
1. Apply power (V
2. Maintain stable conditions for 200µs (MIN).
3. Issue at least three consecutive MRS commands: two dummies or more plus one valid
4.
The RLDRAM must be powered up and initialized in a predefined manner. Operational
procedures other than those specified may result in undefined operations or permanent
damage to the device.
The following sequence is used for power-up:
ages are stable. Apply V
before or at the same time as V
between V
ages approach their nominal levels. CK/CK# must meet V
applied.
while applying NOP conditions to the command pins guarantees that the RLDRAM
will not receive unwanted commands during initialization.
MRS. The purpose of these consecutive MRS commands is to internally reset the logic
of the RLDRAM. Note that
commands. It is recommended that all address pins are held LOW during the dummy
MRS commands.
t
1,024 NOP commands) must be issued prior to normal operation. The sequence of
the eight AUTO REFRESH commands (with respect to the 1,024 NOP commands)
does not matter. As is required for any operation,
REFRESH command and a subsequent VALID command to the same bank. Note that
previous versions of the data sheet required each of these AUTO REFRESH commands
be separated by 2,048 NOP commands. This properly initializes the RLDRAM but is
no longer required.
and all other pins with an output driver, will go HIGH instead of tri-stating. These pins
will remain HIGH until V
avoid bus conflicts during this period.
large external resistor from CS# to V
bus does not receive unwanted commands during this unspecified state.
MRSC after the valid MRS, an AUTO REFRESH command to all 8 banks (along with
ID(DC)
2
on CK/CK# can not be met prior to being applied to the RLDRAM, placing a
Apply NOP conditions to command pins. Ensuring CK/CK# meet V
EXT
and V
EXT
288Mb: x18 2.5V V
, V
DD
DD
DDQ
, the chip starts the power-up sequence only after both volt-
DD
, V
DD
t
DDQ
and V
40
MRSC does not need to be met between these consecutive
before V
is at the same level as V
, V
EXT
REF
REF
DD
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
before or at the same time as V
, V
and V
. However, when doing this, the Ds, DM, Qs,
is a viable option for ensuring the command
TT
EXT
) and start clock as soon as the supply volt-
, 1.8V V
TT
. Although there is no timing relation
t
RC must be met between an AUTO
DDQ
DD
. Care should be taken to
, HSTL, SIO, RLDRAM II
©2003Micron Technology, Inc. All rights reserved.
ID(DC)
DDQ
prior to being
Operations
.
1
Apply V
ID(DC)
DDQ