S25FL016A0LMFI011

Manufacturer Part NumberS25FL016A0LMFI011
ManufacturerSpansion Inc.
S25FL016A0LMFI011 datasheet
 


Specifications of S25FL016A0LMFI011

Cell TypeNORDensity16Mb
Access Time (max)10nsInterface TypeSerial (SPI)
Boot TypeNot RequiredAddress Bus1b
Operating Supply Voltage (typ)3/3.3VOperating Temp Range-40C to 85C
Package TypeSOIC WProgram/erase Volt (typ)2.7 to 3.6V
Sync/asyncSynchronousOperating Temperature ClassificationIndustrial
Operating Supply Voltage (min)2.7VOperating Supply Voltage (max)3.6V
Word Size8bNumber Of Words2M
Supply Current19mAMountingSurface Mount
Pin Count8Lead Free Status / RoHS StatusCompliant
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S25FL016A
16 Megabit CMOS 3.0 Volt Flash Memory
with 50-MHz SPI (Serial Peripheral Interface) Bus
Data Sheet
This product has been retired and is not recommended for designs. For new and current designs,
S25FL032P supercedes S25FL016A. This is the factory-recommended migration path. Please refer to the
S25FL032P data sheet for specifications and ordering information.
Availability of this document is retained for reference and historical purposes only.
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume
such that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.
Publication Number S25FL016A_00
Revision C
Amendment 4
S25FL016A Cover Sheet
Issue Date February 27, 2009

S25FL016A0LMFI011 Summary of contents

  • Page 1

    ... Availability of this document is retained for reference and historical purposes only. Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur ...

  • Page 2

    ... Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.” ...

  • Page 3

    ... Publication Number S25FL016A_00 This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient pro- duction volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid com- binations offered may occur ...

  • Page 4

    Table of Contents Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 5

    Figures Figure 2.1 16-pin Plastic Small Outline Package (SO ...

  • Page 6

    Tables Table 5.1 S25FL016A Valid Combinations Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 7

    Block Diagram SRAM Logic 2. Connection Diagrams February 27, 2009 S25FL016A_00_C4 Array - L RD DATA PATH IO Figure 2.1 16-pin Plastic Small Outline Package (SO) 16 HOLD ...

  • Page 8

    Figure 2.2 8-pin Plastic Small Outline Package (SO CS GND Figure 2 8-Pin WSON Package ( ...

  • Page 9

    Input/Output Descriptions Signal I/O SO Output SI Input SCK Input CS# Input HOLD# Input W# Input V Input CC GND Input 4. Logic Symbol February 27, 2009 S25FL016A_00_C4 Description Signal ...

  • Page 10

    ... A for standard package (non-Pb free); F for Pb-free package DEVICE FAMILY S25FL ® Spansion Memory 3.0 Volt-only, Serial Peripheral Interface (SPI) Flash Memory Table 5.1 S25FL016A Valid Combinations Table S25FL016A Valid Combinations Package & Speed Option Temperature MAI, MFI 0L NAI, NFI S25FL016A PACKING TYPE (Note Tray ...

  • Page 11

    ... Spansion SPI Modes A microcontroller can use either of its two SPI modes to control Spansion SPI Flash memory devices: CPOL = 0, CPHA = 0 (Mode 0) CPOL = 1, CPHA = 1 (Mode 3) Input data is latched in on the rising edge of SCK, and output data is available from the falling edge of SCK for both modes ...

  • Page 12

    Device Operations All Spansion SPI devices (S25FL-A) accept and output data in bytes (8 bits at a time). 7.1 Byte or Page Programming Programming data requires two commands: Write Enable (WREN), which is one byte, and a Page Program ...

  • Page 13

    ... Data Protection Modes Spansion SPI Flash memory devices provide the following data protection methods: The Write Enable (WREN) command: Must be written prior to any command that modifies data. The WREN command sets the Write Enable Latch (WEL) bit. The WEL bit resets (disables writes) on power-up or after the device completes the following commands: – ...

  • Page 14

    ... Each page or byte can be individually programmed (bits are changed from 1 to 0). The data is erased (bits are changed from sector- or device-wide basis using the commands. sector. The complete set of sectors comprises the memory array of the Flash device. Each Device has 2,097,152 ...

  • Page 15

    Sector SA31 SA30 SA29 SA28 SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 February 27, 2009 S25FL016A_00_C4 ...

  • Page 16

    Command Definitions The host system must shift all commands, addresses, and data in and out of the device, beginning with the most significant bit. On the first rising edge of SCK after CS# is driven low, the device accepts ...

  • Page 17

    Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ command reads data from the memory array at the frequency (f input, with a maximum speed of 50 MHz. The host system must first select the device by driving CS# ...

  • Page 18

    Figure 9.3 Read Identification (RDID) Command Sequence and Data-Out Sequence CS# 0 Mode 3 SCK Mode 0 SI Hi-Z SO Manufacturer Identification 9.4 Write Enable (WREN) The Write Enable (WREN) command (see enables the device to accept a Write Status ...

  • Page 19

    Write Disable (WRDI) The Write Disable (WRDI) command (see disables the device from accepting a Write Status Register, program, or erase command. The host system must first drive CS# low, write the WRDI command, and then drive CS# high. ...

  • Page 20

    ... The WRSR command cannot change the state of the Write Enable Latch (bit 1). The WREN command must be used for that purpose. Bit status bit controlled internally by the Flash device. Bits 6 and 5 are always read as 0 and have no user significance. The WRSR command also controls the value of the Status Register Write Disable (SRWD) bit. The SRWD bit and W# together place the device in the Hardware Protected Mode (HPM) ...

  • Page 21

    W# SRWD Signal Bit Mode 1 1 Software 1 0 Protected (SPM Hardware 0 1 Protected (HPM) Note As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in ...

  • Page 22

    CS# Mode 3 SCK Mode SCK MSB 9.9 Sector Erase (SE) The Sector Erase (SE) command sets all bits at all addresses within a specified sector to a logic 1. A WREN ...

  • Page 23

    Bulk Erase (BE) The Bulk Erase (BE) command sets all the bits within the entire memory array to logic 1s. A WREN command is required prior to writing the PP command. The host system must drive CS# low, and ...

  • Page 24

    CS# Mode 3 SCK Mode 0 SI Hi-Z SO 9.12 Release from Deep Power Down (RES) The device requires the Release from Deep Power Down (RES) command to exit the Deep Power Down mode. When the device is in the ...

  • Page 25

    Release from Deep Power Down and Read Electronic Signature (RES) The device features an 8-bit Electronic Signature, which can be read using the RES command. See Figure 9.13 and Table 9.4 on page 25 Signature is not to be ...

  • Page 26

    Power-up and Power-down During power-up and power-down, certain conditions must be observed. CS# must follow the voltage applied and must not be driven low to select the device until V CC (see Figure 10.1 and At ...

  • Page 27

    Absolute Maximum Ratings Do not stress the device beyond the ratings listed in this section, or serious, permanent damage to the device may result. These are stress ratings only and device operation at these or any other conditions beyond ...

  • Page 28

    DC Characteristics This section summarizes the DC Characteristics of the device. Designers should check that the operating conditions in their circuit match the measurement conditions specified in the Test Specifications in on page 28, when relying on the quoted ...

  • Page 29

    AC Characteristics Symbol (Notes) F SCK Clock Frequency READ command SCK SCK Clock Frequency for: F SCK FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI, RDSR, WRSR t Clock Rise Time (Slew Rate) CRT t Clock Fall Time (Slew ...

  • Page 30

    CS# t CSH SCK SI Hi-Z SO CS# SCK CS# SCK SO SI HOLD Figure 16.1 SPI Mode 0 (0,0) Input Timing t CSS t ...

  • Page 31

    Figure 16.4 Write Protect Setup and Hold Timing during WRSR when SRWD=1 W# CS# SCK SI Hi-Z SO February 27, 2009 S25FL016A_00_C4 WPS S25FL016A t WPH 31 ...

  • Page 32

    ... THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE 0.457 OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF 0.241 MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH. BUT INCLUDING ANY MISMATCH BETWEEN THE TOP 0.203 AND BOTTOM OF THE PLASTIC BODY. 5.283 BSC 5 ...

  • Page 33

    ... THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE 0.48 OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF 0.33 MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH. BUT INCLUDING ANY MISMATCH BETWEEN THE TOP 0.30 AND BOTTOM OF THE PLASTIC BODY. 5. ...

  • Page 34

    WSON 8-contact ( mm) No-Lead Package D N 0.30 DIA TYP 0. TOP VIEW 2X 0. 0.05 C SEATING PLANE A1 L e/2 QUAD FLAT NO LEAD ...

  • Page 35

    Revision History Section Revision A (July 13, 2004) Global Initial release. Revision A1 (September 13, 2004) Connection Diagrams Added the WSON 6x8mm pin out. Changed OPN to reflect Device technology identification change from for CS99S MirrorBit ...

  • Page 36

    S25FL016A S25FL016A_00_C4 February 27, 2009 ...

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    ... Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2004-2009 Spansion Inc. All rights reserved. Spansion ™ ™ ...