MT45W1MW16BDGB-708 WT

Manufacturer Part NumberMT45W1MW16BDGB-708 WT
ManufacturerMicron Technology Inc
MT45W1MW16BDGB-708 WT datasheet
 

Specifications of MT45W1MW16BDGB-708 WT

Operating Temperature (max)85CMountingSurface Mount
Operating Temperature ClassificationCommercialLead Free Status / RoHS StatusCompliant
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Async/Page/Burst CellularRAM™ Memory
MT45W1MW16BDGB
Features
• Single device supports asynchronous, page, and
burst operations
• Random access time: 70ns
• V
, V
Q voltages:
CC
CC
– 1.7–1.95V V
CC
1
– 1.7–3.6V
V
Q
CC
• Page mode read access
– Sixteen-word page size
– Interpage read access: 70ns
– Intrapage read access: 20ns
• Burst mode write access: continuous burst
• Burst mode read access:
– 4, 8, or 16 words, or continuous burst
t
– MAX clock rate: 104 MHz (
CLK = 9.62ns)
– Burst initial latency: 39ns (4 clocks) @ 104 MHz
t
ACLK: 7ns @ 104 MHz
• Low power consumption
– Asynchronous read: <20mA
– Intrapage read: <15mA
– Intrapage read initial access, burst read:
– (39ns [4 clocks] @ 104 MHz) < 35mA
– Continuous burst read: <28mA
– Standby: 70µA
– Deep power-down: <10µA (TYP @ 25°C)
• Low-power features
– Temperature-compensated refresh (TCR)
– On-chip temperature sensor
– Partial-array refresh (PAR)
– Deep power-down (DPD) mode
Options
• Configuration
– 1 Meg x 16
• Package
– 54-ball VFBGA (“green”)
• Access time
– 70ns access
• Frequency
– 80 MHz
– 104 MHz
PDF: 09005aef81cb58ed/Source: 09005aef81c7a667
16mb_burst_cr1_0_p23z_1.fm - Rev. H 4/08 EN
Products and specifications discussed herein are subject to change by Micron without notice.
16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Figure 1:
Options (continued)
• Standby power
Designator
– Standard
• Operating temperature range
MT45W1MW16BD
– Wireless (–30°C to +85°C)
– Industrial (–40°C to +85°C)
GB
Notes: 1. 3.6V I/O and –30°C exceed the CellularRAM
-70
8
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1
54-Ball VFBGA
1
2
3
4
5
A
A1
LB#
OE#
A0
A2
B
DQ8
UB#
A3
A4
CE#
C
DQ9
DQ10
A5
A6
DQ1
D
V
Q
DQ11
A17
A7
DQ3
SS
E
V
Q
DQ12
NC
A16
DQ4
CC
F
DQ14
DQ13
A14
A15
DQ5
G
DQ15
A19
A12
A13
WE#
H
A18
A8
A9
A10
A11
J
WAIT
CLK
ADV#
NC
NC
Top View
(Ball Down)
Designator
Workgroup 1.0 specifications.
2. Contact factory.
Part Number Example:
MT45W1MW16BDGB-701WT
©2005 Micron Technology, Inc. All rights reserved.
Features
6
CRE
DQ0
DQ2
V
CC
V
SS
DQ6
DQ7
NC
NC
None
1
WT
2
IT

MT45W1MW16BDGB-708 WT Summary of contents

  • Page 1

    ... DQ15 A19 A12 A13 WE# H A18 A8 A9 A10 A11 J WAIT CLK ADV Top View (Ball Down) Designator Workgroup 1.0 specifications. 2. Contact factory. Part Number Example: MT45W1MW16BDGB-701WT ©2005 Micron Technology, Inc. All rights reserved. Features 6 CRE DQ0 DQ2 DQ6 DQ7 NC NC None ...

  • Page 2

    Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 3

    List of Figures Figure 1: 54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 4

    List of Tables Table 1: VFBGA Ball Descriptions ...

  • Page 5

    ... General Description Micron low-power, portable applications. The MT45W1MW16BDGB is a 16Mb DRAM core device organized as 1 Meg x 16 bits. This device includes an industry-standard burst mode Flash interface that dramatically increases read/write bandwidth compared with other low-power SRAM or Pseudo SRAM offerings. For seamless operation on a burst Flash bus, CellularRAM products incorporate a trans- parent self-refresh mechanism ...

  • Page 6

    Functional Block Diagrams Figure 2: Functional Block Diagram – 1 Meg x 16 A[19:0] CE# WE# OE# CLK Control ADV# Logic CRE WAIT LB# UB# Note: Functional block diagrams illustrate simplified device operation. See truth table, ball descriptions, and timing ...

  • Page 7

    Ball Descriptions Table 1: VFBGA Ball Descriptions VFBGA Assignment Symbol Type G2, H1, D3, E4, A[19:0] Input F4, F3, G4, G3, H5, H4, H3, H2, D4, C4, C3, B4, B3, A5, A4 CLK Input J3 ADV# Input A6 ...

  • Page 8

    Bus Operations Table 2: Bus Operations – Asynchronous Mode Mode Power Read Active Write Active Standby Standby Idle No operation Active Configuration Register DPD Deep power-down Table 3: Bus Operations – Burst Mode Mode Power CLK Async read Active Async ...

  • Page 9

    Part Numbering Information Micron CellularRAM devices are available in several different configurations and densi- ties (see Figure 3). Figure 3: Part Number Chart Micron Technology Product Family 45 = PSRAM/CellularRAM Memory Operating Core Voltage ...

  • Page 10

    ... Functional Description In general, the MT45W1MW16BDGB devices are high-density alternatives to SRAM and Pseudo SRAM products, popular in low-power, portable applications. The MT45W1MW16BDGB contains a 16,777,216-bit DRAM core organized as 1,048,576 addresses by 16 bits. This device implements the same high-speed bus interface found on burst mode Flash products. ...

  • Page 11

    Figure 5: READ Operation (ADV = LOW) CE# OE# WE# ADDRESS DATA LB#/UB# Note: ADV must remain LOW for page mode operation. Figure 6: WRITE Operation (ADV = LOW) CE# OE# WE# ADDRESS DATA LB#/UB# Page Mode READ Operation Page ...

  • Page 12

    The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer t than Figure 7: Page Mode READ Operation (ADV = LOW) CE# OE# WE# ADDRESS DATA LB#/UB# Burst Mode Operation Burst mode operations enable high-speed ...

  • Page 13

    The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer t than will cause CE# to remain LOW for longer than burst restarted with a new CE# LOW/ADV# LOW cycle. Figure 8: Burst Mode READ ...

  • Page 14

    Figure 9: Burst Mode WRITE (4-word Burst) CLK ADDRESS A[19:0] ADV# CE# OE# WE# WAIT DQ[15:0] LB#/UB# WRITE Burst Identified (WE# = LOW) Note: Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. PDF: ...

  • Page 15

    Mixed-Mode Operation The device can support a combination of synchronous READ and asynchronous WRITE operations when the BCR is configured for synchronous operation. The asynchronous WRITE operation requires that the clock (CLK) be held static LOW or HIGH during the ...

  • Page 16

    RAM array and the internal value will remain unchanged. During an asynchronous WRITE cycle, the data to be written is latched on the rising edge of CE#, WE#, LB#, or ...

  • Page 17

    Figure 12: Refresh Collision During WRITE Operation V IH CLK VALID A[19:0] ADDRESS ADV ...

  • Page 18

    Low-Power Operation Standby Mode Operation During standby, the device current consumption is reduced to the level necessary to perform the DRAM refresh operation. Standby operation occurs when CE# is HIGH. The device will enter a reduced power state upon completion ...

  • Page 19

    Configuration Registers Two user-accessible configuration registers define the device operation. The bus config- uration register (BCR) defines how the CellularRAM interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh ...

  • Page 20

    Figure 14: Configuration Register WRITE in Synchronous Mode Followed by READ ARRAY Operation CLK Latch Control Register Value A[18:0] OPCODE A19 t SP CRE ADV CSP CE# OE# ...

  • Page 21

    Software Access Software access of the configuration registers uses a sequence of asynchronous READ and asynchronous WRITE operations. The contents of the configuration registers can be read or modified using the software sequence. The configuration registers are loaded using a ...

  • Page 22

    Figure 16: Read Configuration Register ADDRESS CE# OE# WE# LB#/UB# DATA Note: If the data present when WE# falls is not 0000h or 0001h possible that the maximum address will be overwritten. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. ...

  • Page 23

    Bus Configuration Register The BCR defines how the CellularRAM device interacts with the system memory bus. Page mode operation is enabled by a bit contained in the RCR. Figure 17 describes the control bits in the BCR. At power-up, the ...

  • Page 24

    Table 4: Sequence and Burst Length 4-Word Starting Burst Burst Wrap Address Length BCR[3] Wrap (Decimal) Linear 0 0-1-2-3 1 1-2-3-0 2 2-3-0-1 3 3-0-1 Yes 6 7 ... 0-1-2-3 1 1-2-3-4 2 2-3-4-5 ...

  • Page 25

    Output Impedance (BCR[5]) Default = Outputs Use Full Drive Strength The output driver strength can be altered to adjust for different data bus loading scenarios. The reduced-strength option should be more than adequate in stacked chip (Flash + CellularRAM) environments ...

  • Page 26

    Figure 20: WAIT Configuration During Burst Operation CLK WAIT WAIT DQ[15:0] Note: Non-default BCR setting for WAIT during BURST operation: WAIT active LOW. Latency Counter (BCR[13:11]) Default = Three-Clock Latency The latency counter bits determine how many clocks occur between ...

  • Page 27

    Refresh Configuration Register The refresh configuration register (RCR) defines how the CellularRAM device performs its transparent self refresh. Altering the refresh parameters can dramatically reduce current consumption during standby mode. Page mode control is also embedded into the RCR. Figure ...

  • Page 28

    Table 6: 16Mb Address Patterns for PAR (RCR[ RCR[2] RCR[1] RCR[ Deep Power-Down (RCR[4]) ...

  • Page 29

    Electrical Characteristics Table 7: Absolute Maximum Ratings Voltage to any ball except Voltage on V Voltage on V Storage temperature (plastic) Operating temperature (case) Wireless Industrial Soldering temperature and time 10 seconds (solder ball only) Notes: ...

  • Page 30

    Table 8: Electrical Characteristics and Operating Conditions Wireless temperature Description Supply voltage I/O supply voltage Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current Output leakage current Operating Current Asynchronous random READ/ WRITE Asynchronous ...

  • Page 31

    ... Maximum and Typical Standby Currents The following table and figure refer to the maximum and typical standby currents for the MT45W1MW16BDGB device. The typical values shown in Figure 23 are measured with the default on-chip temperature sensor control enabled. The maximum values shown in Table 9 are measured with the relevant TCR bits set in the configuration register. ...

  • Page 32

    Table 10: Deep Power-Down Specifications Description Deep power-down Table 11: Capacitance Description Input capacitance Input/output capacitance (DQ) Notes: 1. These parameters are verified in device characterization and are not 100 percent tested. Figure 24: AC Input/Output Reference Waveform V CC ...

  • Page 33

    Timing Requirements Table 12: Asynchronous READ Cycle Timing Requirements 1 Parameter Address access time ADV# access time Page access time Address hold from ADV# HIGH Address setup to ADV# HIGH LB#/UB# access time LB#/UB# disable to DQ High-Z output LB#/UB# ...

  • Page 34

    Table 13: Burst READ Cycle Timing Requirements 1 Parameter Burst to READ access time CLK to output delay Burst OE# LOW to output delay CE# HIGH between subsequent burst and mixed-mode operations Maximum CE# pulse width CE# LOW to WAIT ...

  • Page 35

    Table 14: Asynchronous WRITE Cycle Timing Requirements Parameter Address and ADV# LOW setup time Address hold from ADV# going HIGH Address setup to ADV# going HIGH Address valid to end of WRITE LB#/UB# select to end of WRITE CE# LOW ...

  • Page 36

    Table 15: Burst WRITE Cycle Timing Requirements Parameter CE# HIGH between subsequent burst and mixed-mode operations Maximum CE# pulse width CE# LOW to WAIT valid Clock period CE# setup to CLK active edge Hold time from active CLK edge Chip ...

  • Page 37

    Timing Diagrams Figure 27: Asynchronous READ A[19:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] WAIT PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory VALID ADDRESS V IL ...

  • Page 38

    Figure 28: Asynchronous READ Using ADV# A[19:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] WAIT PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory V IH VALID ADDRESS ...

  • Page 39

    Figure 29: Page Mode READ A[19:4] A[3:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] WAIT PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory VALID ADDRESS V IL ...

  • Page 40

    Figure 30: Single-Access Burst READ Operation V IH CLK A[19:0] VALID ADDRESS ADV CSP ...

  • Page 41

    Figure 31: 4-Word Burst READ Operation V IH CLK A[19:0] VALID ADDRESS ADV CSP ...

  • Page 42

    Figure 32: READ Burst Suspend V IH CLK VALID A[19:0] V ADDRESS ADV CSP OE# ...

  • Page 43

    Figure 33: Continuous Burst READ Showing an Output Delay with BCR[ for End-of-Row Condition V IH CLK CLK V IH A[19: ADV LB#/UB ...

  • Page 44

    Figure 34: CE#-Controlled Asynchronous WRITE A[19:0] ADV# LB#/UB# OE# WE# DQ[15:0] DQ[15:0] OUT WAIT PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory VALID ADDRESS V IL ...

  • Page 45

    Figure 35: LB#/UB#-Controlled Asynchronous WRITE A[19:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] DQ[15:0] OUT WAIT PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory VALID ADDRESS V ...

  • Page 46

    Figure 36: WE#-Controlled Asynchronous WRITE A[19:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] DQ[15:0] OUT WAIT PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory V IH VALID ADDRESS ...

  • Page 47

    Figure 37: Asynchronous WRITE Using ADV# A[19:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] DQ[15:0] OUT WAIT PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory V IH VALID ADDRESS V IL ...

  • Page 48

    Figure 38: Burst WRITE Operation V IH CLK A[19:0] VALID ADDRESS ADV LB#/UB CSP V IH CE# ...

  • Page 49

    Figure 39: Continuous Burst WRITE Showing an Output Delay with BCR[ for End-of-Row Condition V IH CLK CLK V IH A[19: ADV LB#/UB ...

  • Page 50

    Figure 40: Burst WRITE Followed by Burst READ t CLK V IH CLK A[19:0] VALID V ADDRESS ADV LB#/UB ...

  • Page 51

    Figure 41: Asynchronous WRITE Followed by Burst READ V IH CLK A[19:0] VALID ADDRESS VALID ADDRESS AVS t AVH VPH V IH ADV ...

  • Page 52

    Figure 42: Asynchronous WRITE Followed by Burst READ – ADV# LOW V IH CLK A[19:0] VALID ADDRESS VALID ADDRESS AVS t AVH VPH V IH ADV# ...

  • Page 53

    Figure 43: Burst READ Followed by Asynchronous WRITE (WE#-Controlled CLK A[19:0] VALID ADDRESS ADV CSP V IH CE# V ...

  • Page 54

    Figure 44: Burst READ Followed by Asynchronous WRITE Using ADV CLK A[19:0] VALID ADDRESS ADV CSP ...

  • Page 55

    Figure 45: Asynchronous WRITE Followed by Asynchronous READ – ADV# LOW V IH A[19:0] VALID ADDRESS ADV LB#/ ...

  • Page 56

    Figure 46: Asynchronous WRITE Followed by Asynchronous READ A[19:0] ADV# LB#/UB# CE# OE# WE# WAIT DQ[15:0] IN/OUT Notes: 1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns ( required after CE#-controlled WRITEs. ...

  • Page 57

    ... All dimensions in millimeters; MAX/MIN or typical, as noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. The MT45W1MW16BDGB uses “green” packaging. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc ...

  • Page 58

    Revision History Rev. H, Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 59

    Page 1, Figure 1: changed E3 ball color to white • Page 1: changed multiple “-” to “–” for negative numbers (per style) • Eliminated holdover references to dual parts (pgs. 10 and 30) • Updated to state that ...