ISP1160BM/01,151 NXP Semiconductors, ISP1160BM/01,151 Datasheet - Page 52

• Manufacturer Part Number: ISP1160BM/01,151
• Manufacturer: NXP Semiconductors

Specifications of ISP1160BM/01,151

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Table 34.
ISP1160-01_7
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcRhPortStatus[1:2] register: bit allocation
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
Table 35.
Bit
31 to 21
20
19
18
17
reserved
reserved
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
HcRshPortStatus[1:2] register: bit description
Symbol
-
PRSC
OCIC
PSSC
PESC
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Rev. 07 — 29 September 2009
reserved
Description
reserved
PortResetStatusChange: This bit is set at the end of the 10 ms port
reset signal. The HCD writes a logic 1 to clear this bit. Writing a logic 0
has no effect.
0 — port reset is not complete
1 — port reset is complete
PortOverCurrentIndicatorChange: This bit is valid only if
overcurrent conditions are reported on a per-port basis. This bit is set
when Root Hub changes the PortOverCurrentIndicator bit. The HCD
writes a logic 1 to clear this bit. Writing a logic 0 has no effect.
0 — no change in PortOverCurrentIndicator
1 — PortOverCurrentIndicator has changed
PortSuspendStatusChange: This bit is set when the full resume
sequence has been completed. This sequence includes the 20 s
resume pulse, LS EOP, and 3 ms resynchronization delay. The HCD
writes a logic 1 to clear this bit. Writing a logic 0 has no effect. This bit
is also cleared when ResetStatusChange is set.
0 — resume is not completed
1 — resume is completed
PortEnableStatusChange: This bit is set when hardware events
cause the PortEnableStatus bit to be cleared. Changes from HCD
writes do not set this bit. The HCD writes a logic 1 to clear this bit.
Writing a logic 0 has no effect.
0 — no change in PortEnableStatus
1 — change in PortEnableStatus
PRSC
PRS
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
reserved
OCIC
POCI
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
PSSC
Embedded USB host controller
PSS
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
ISP1160/01
© ST-ERICSSON 2009. All rights reserved.
PESC
LSDA
R/W
R/W
R/W
PES
R/W
25
17
0
0
9
0
1
0
CSC
CCS
PPS
R/W
R/W
R/W
R/W
24
16
0
0
8
0
0
0
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