ISP1160BM/01,151 NXP Semiconductors, ISP1160BM/01,151 Datasheet - Page 65

• Manufacturer Part Number: ISP1160BM/01,151
• Manufacturer: NXP Semiconductors

Specifications of ISP1160BM/01,151

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Table 62.
ISP1160-01_7
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcITLBufferPort register: bit allocation
10.6.6 HcITLBufferPort register (R/W: 40H/C0H)
10.6.7 HcATLBufferPort register (R/W: 41H/C1H)
R/W
R/W
15
R
7
0
0
7
0
Table 61.
This is the ITL buffer RAM read/write port. The bits 15:8 contain the data byte that comes
from the ITL buffer RAM’s even address. The bits 7:0 contain the data byte that comes
from the ITL buffer RAM’s odd address.
Code (Hex): 40 — read
Code (Hex): C0 — write
Table 63.
The HCD must set the byte count into the HcTransferCounter register and check the
HcBufferStatus register before reading from or writing to the buffer. The HCD must write
the command (40H to read, C0H to write) once only, and then read or write both bytes of
the data word. After every read/write, the pointer of ITL buffer RAM will be automatically
increased by two to point to the next data word until it reaches the value of the
HcTransferCounter register; otherwise, an internal EOT signal is not generated to set bit 2
(AllEOTInterrupt) of the HcμPInterrupt register and update the HcBufferStatus register.
The HCD must take care of the fact that the internal buffer RAM is organized in bytes. The
HCD must write the byte count into the HcTransferCounter register, but the HCD reads or
writes the buffer RAM by 16 bits (by 1 word).
This is the ATL buffer RAM read/write port. Bits 15 to 8 contain the data byte that comes
from the Acknowledged Transfer List (ATL) buffer RAM’s odd address. Bits 7 to 0 contain
the data byte that comes from the ATL buffer RAM’s even address.
Bit
15 to 0
Bit
15 to 0
R/W
R/W
14
R
6
0
0
6
0
Symbol
RdITL1BufferLength[15:0]
Symbol
DataWord[15:0]
HcReadBackITL1Length register: bit description
HcITLBufferPort register: bit description
R/W
R/W
13
R
5
0
0
5
0
Rev. 07 — 29 September 2009
RdITL1BufferLength[7:0]
R/W
R/W
12
Description
Read/write ITL buffer RAM’s two data bytes.
DataWord[15:8]
R
4
0
0
4
0
DataWord[7:0]
The number of bytes for ITL1 data to be read back by the
Description
microprocessor.
R/W
R/W
11
R
3
0
0
3
0
Embedded USB host controller
R/W
R/W
10
R
2
0
0
2
0
ISP1160/01
© ST-ERICSSON 2009. All rights reserved.
R/W
R/W
R
1
0
9
0
1
0
R/W
R/W
R
0
0
8
0
0
0
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