ISP1161A1BD,151 STEricsson, ISP1161A1BD,151 Datasheet - Page 101

• Manufacturer Part Number: ISP1161A1BD,151
• Manufacturer: STEricsson

Specifications of ISP1161A1BD,151

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 92.
ISP1161A1_4
Product data sheet
Bit
Symbol
Reset
Access
DcEndpointStatus register: bit allocation
13.2.3 Stall Endpoint/Unstall Endpoint (40H–4FH/80H—8FH)
EPSTAL
R
7
0
Table 93.
These commands are used to stall or unstall an endpoint. The commands modify the
content of the DcEndpointStatus register (see
A stalled control endpoint is automatically unstalled when it receives a SETUP token,
regardless of the packet content. If the endpoint should stay in its stalled state, the
microprocessor can re-stall it with the Stall Endpoint command.
When a stalled endpoint is unstalled (either by the Unstall Endpoint command or by
receiving a SETUP token), it is also re-initialized. This flushes the buffer: if it is an OUT
buffer it waits for a DATA 0 PID, if it is an IN buffer it writes a DATA 0 PID.
Code (Hex): 40 to 4F — stall (control OUT, control IN, endpoint 1 to 14)
Code (Hex): 80 to 8F — unstall (control OUT, control IN, endpoint 1 to 14)
Transaction — none
Bit
7
6
5
4
3
2
1
0
EPFULL1
R
6
0
DcEndpointStatus register: bit description
Symbol
EPSTAL
EPFULL1
EPFULL0
DATA_PID
OVERWRITE
SETUPT
CPUBUF
-
EPFULL0
R
5
0
Rev. 04 — 29 January 2009
Description
This bit indicates whether the endpoint is stalled or not (1 = stalled,
0 = not stalled).
Set to logic 1 by a Stall Endpoint command and cleared to logic 0 by
an Unstall Endpoint command. The endpoint is automatically
unstalled upon reception of a SETUP token.
A logic 1 indicates that the secondary endpoint buffer is full.
A logic 1 indicates that the primary endpoint buffer is full.
This bit indicates the data PID of the next packet (0 = DATA PID,
1 = DATA1 PID).
This bit is set by hardware, a logic 1 indicating that a new Setup
packet has overwritten the previous set-up information, before it
was acknowledged or before the endpoint was stalled. If writing the
set-up data has finished, this bit is cleared by a read action.
Firmware must check this bit before sending an Acknowledge
Setup command or stalling the endpoint. Upon reading a logic 1,
the firmware must stop ongoing set-up actions and wait for a new
Setup packet.
A logic 1 indicates that the buffer contains a Setup packet.
This bit indicates which buffer is currently selected for CPU access
(0 = primary buffer, 1 = secondary buffer).
reserved
DATA_PID
R
4
0
WRITE
OVER
USB single-chip host and device controller
R
3
0
Table
92).
SETUPT
R
2
0
ISP1161A1
CPUBUF
© ST-NXP Wireless 2009. All rights reserved.
R
1
0
reserved
100 of 140
R
0
0