ISP1161A1BD,151 STEricsson, ISP1161A1BD,151 Datasheet - Page 108

no-image

ISP1161A1BD,151

Manufacturer Part Number
ISP1161A1BD,151
Description
Manufacturer
STEricsson
Datasheet

Specifications of ISP1161A1BD,151

Lead Free Status / RoHS Status
Supplier Unconfirmed
ISP1161A1_4
Product data sheet
Table 109. DcInterrupt register: bit description
Bit
6
5
4
3
2
1
0
Symbol
SP_EOT
PSOF
SOF
EOT
SUSPND
RESUME
RESET
Rev. 04 — 29 January 2009
Description
A logic 1 indicates that an EOT interrupt has occurred for a short
packet.
A logic 1 indicates that an interrupt is issued every 1 ms because of
the Pseudo SOF; after 3 missed SOFs ‘suspend’ state is entered.
A logic 1 indicates that a SOF condition was detected.
A logic 1 indicates that an internal EOT condition was generated by
the DMA Counter reaching zero.
A logic 1 indicates that an ‘awake’ to ‘suspend’ change of state was
detected on the USB bus.
A logic 1 indicates that a ‘resume’ state was detected.
A logic 1 indicates that a bus reset condition was detected.
USB single-chip host and device controller
…continued
ISP1161A1
© ST-NXP Wireless 2009. All rights reserved.
107 of 140

Related parts for ISP1161A1BD,151