LSISAS1064 LSI, LSISAS1064 Datasheet - Page 143

• Manufacturer Part Number: LSISAS1064
• Manufacturer: LSI

Specifications of LSISAS1064

• Lead Free Status / RoHS Status: Not Compliant

memory [0] low 4-5,
memory [1] high 4-5,
memory [1] low 4-5,
memory read
memory requirements
memory space 2-10,
message passing technology
message queues 2-7,
message signaled interrupts
MFA
minimum grant register
MODE[5:0] 3-10, 3-16,
MOE[1:0]/ 3-8,
MSI 2-16,
MSI mask bits register
MSI message address register
MSI message control register
MSI message data register
MSI message upper address register
MSI pending bits register
MSI-X 2-16,
MSI-X enable 3-14,
MSI-X message control register
MSI-X PBA offset register
MSI-X table offset register
multi-ICE
multiple cache line transfers
multiple message capable
multiple message enable
MWE[1:0]/ 3-8,
N
narrow port
high priority request
reply
capability ID register
enable bit
mask bits
message address
message data
message upper address register
multiple message
next pointer register
pending bits
capability ID register
next pointer register
PBA offset
table offset
4-41
2-25
4-39
2-17
4-39
4-24
4-22
4-30
4-27
4-26
5-6
5-6
4-24
4-23
3-15
4-10
4-11
4-22
4-32
4-22
4-11
Index
Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
2-19
2-8
4-24
5-4
4-41
4-20
4-25
4-16
4-20
4-24
4-21
4-24
4-27
4-22
4-26
4-23
2-15
2-16
2-1
4-21
4-22
4-25
4-23
4-23
NC 3-1,
new capabilities bit
no connect
NVSRAM
NVSRAM or SRAM select
NVSRAM/SRAM installed
NVSRAM_CS/ 3-8,
O
operating conditions
operating free air temperature
P
package drawing 5-18, 5-19,
PAR 3-4,
PAR64 3-4,
parity error
PBA offset
PC2001 system design guide
PCI 2-7,
33 MHz
64-bit 3-14,
66 MHz 3-14, 3-15,
66 MHz capable bit
address/data bus 3-13,
addressing
alias to memory read block command 2-12,
alias to memory write block command
arbitration
arbitration signals
benefits
bus commands
cache line size register
cache mode
CLK
command
2-14
configuration read 2-9, 2-10,
configuration write 2-9, 2-10,
dual address cycle
dual address cycles
I/O read 2-10,
I/O write
I/O write command
interrupt acknowledge 2-10,
memory read
memory read block 2-11, 2-12,
5-8
3-13
2-8
5-3
2-22
4-27
5-8
1-6
4-6
3-1
5-3
2-10
2-15
2-9
3-15
2-10
2-15
2-10
4-7
5-6
2-10
5-2
2-11
3-5
5-8
4-6
2-14
2-11
3-14
2-8
3-14
4-31
2-14
5-20
2-16
5-2
2-11
2-12
2-13
2-14
2-12
IX-5