LSISAS1064 LSI, LSISAS1064 Datasheet - Page 34

• Manufacturer Part Number: LSISAS1064
• Manufacturer: LSI

Specifications of LSISAS1064

• Lead Free Status / RoHS Status: Not Compliant

2.3
2-8
PCI Functional Description
queue consists of the request post FIFO. The reply message queue
consists of both the reply post FIFO and the reply free FIFO. The context
RAM contains the message queues. The Fusion-MPT architecture also
provides a High Priority Request FIFO to provide high priority request
free messages to the host on reads and to accept high priority request
post messages from the host on writes.
Communication using the message queues occurs through request
messages and reply messages. Request message frame descriptors are
pointers to the request message frames and are passed through the
request post FIFO. The request message frame data structure is up to
128 bytes in length and includes a message header and a payload. The
header uniquely identifies the message. The payload contains
information that is specific to the request. Reply message frame
descriptors have one of two formats and are passed through the reply
post FIFO. When indicating the successful completion of a SCSI I/O, the
IOP writes the reply message frame descriptor using the Context Reply
format, which is a message context. If a SCSI I/O does not complete
successfully, the IOP uses the Address Reply format. In this case, the
IOP pops a reply message frame from the reply free FIFO, generates a
reply message describing the error, writes the reply message to system
memory, and writes the address of the reply message frame to the reply
post FIFO. The host can then read the reply message and take the
appropriate action.
The doorbell mechanism provides both a communication path that
interrupts the host system device driver and an alternative
communication path to the message queues. Since data transport
through the system doorbell occurs a single Dword at a time, use the
LSISAS1064 message queues for normal operation and data transport.
The host PCI interface complies with the PCI Local Bus Specification,
Version 3.0 and the PCI-X Addendum to the PCI Local Bus Specification,
Revision 2.0. The LSISAS1064 supports a 133 MHz, 64-bit PCI-X bus.
The LSISAS1064 provides support for 64-bit addressing with Dual
Address Cycle (DAC). The LSISAS1064 does not support 5 V PCI
signaling.
Functional Description
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