MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 238

• Manufacturer Part Number: MC908AP32CFBE
• Manufacturer: Freescale

Specifications of MC908AP32CFBE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

Multi-Master IIC Interface (MMIIC)
14.6.3
MMALIF — Arbitration Loss Interrupt Flag
MMNAKIF — No AcKnowledge Interrupt Flag (Master Mode)
MMBB — MMIIC Bus Busy Flag
MMAST — MMIIC Master Control
236
Under normal operation, the user software should clear MMTXAK bit before setting MMCRCBYTE bit
to ensure that an acknowledge signal is sent when no CRC error is detected.
The MMCRCBYTE bit should not be set in transmit mode. This bit is cleared by the next START signal.
Reset also clears this bit.
This flag is set when software attempt to set MMAST but the MMBB has been set by detecting the start
condition on the lines or when the MMIIC is transmitting a "1" to SDA line but detected a "0" from SDA
line in master mode — an arbitration loss. This bit generates an interrupt request to the CPU if the
MMIEN bit in MMCR1 is set. This bit is cleared by writing "0" to it or by reset.
This flag is only set in master mode (MMAST = 1) when there is no acknowledge bit detected after one
data byte or calling address is transferred. This flag also clears MMAST. MMNAKIF generates an
interrupt request to CPU if the MMIEN bit in MMCR1 is set. This bit is cleared by writing "0" to it or by
reset.
This flag is set after a start condition is detected (bus busy), and is cleared when a stop condition (bus
idle) is detected or the MMIIC is disabled. Reset clears this bit.
This bit is set to initiate a master mode transfer. In master mode, the module generates a start
condition to the SDA and SCL lines, followed by sending the calling address stored in MMADR.
When the MMAST bit is cleared by MMNAKIF set (no acknowledge) or by software, the module
generates the stop condition to the lines after the current byte is transmitted.
If an arbitration loss occurs (MMALIF = 1), the module reverts to slave mode by clearing MMAST, and
releasing SDA and SCL lines immediately.
This bit is cleared by writing "0" to it or by reset.
1 = Next receiving byte is the packet error checking (PEC) data
0 = Next receiving byte is not PEC data
1 = Lost arbitration in master mode
0 = No arbitration lost
1 = No acknowledge bit detected
0 = Acknowledge bit detected
1 = Start condition detected
0 = Stop condition detected or MMIIC is disabled
1 = Master mode operation
0 = Slave mode operation
MMIIC
Address:
Reset:
Read:
Write:
Control Register 2 (MMCR2)
MMALIF
$004A
Bit 7
0
0
Figure 14-6. MMIIC Control Register 2 (MMCR2)
MMNAKIF
= Unimplemented
6
0
0
MC68HC908AP Family Data Sheet, Rev. 4
MMBB
5
0
MMAST
4
0
MMRW
3
0
2
0
0
1
0
0
Freescale Semiconductor
MMCRCEF
Unaffected
Bit 0