MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 294

• Manufacturer Part Number: MC908AP32CFBE
• Manufacturer: Freescale

Specifications of MC908AP32CFBE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

Break Module (BRK)
The following events can cause a break interrupt to occur:
When a CPU-generated address matches the contents of the break address registers, the break interrupt
begins after the CPU completes its current instruction. A return-from-interrupt instruction (RTI) in the
break routine ends the break interrupt and returns the MCU to normal operation.
structure of the break module.
21.3.1 Flag Protection During Break Interrupts
The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during
the break state.
21.3.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
21.3.3 TIMI and TIM2 During Break Interrupts
A break interrupt stops the timer counters.
21.3.4 COP During Break Interrupts
The COP is disabled during a break interrupt when V
21.4 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
292
•
•
•
•
A CPU-generated address (the address in the program counter) matches the contents of the break
address registers.
Software writes a logic 1 to the BRKA bit in the break status and control register.
Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC and $FFFD
($FEFC and $FEFD in monitor mode)
IAB15–IAB0
Figure 21-2. Break Module Block Diagram
IAB15–IAB8
IAB7–IAB0
MC68HC908AP Family Data Sheet, Rev. 4
BREAK ADDRESS REGISTER HIGH
BREAK ADDRESS REGISTER LOW
8-BIT COMPARATOR
8-BIT COMPARATOR
TST
is present on the RST pin.
CONTROL
Figure 21-2
BREAK
Freescale Semiconductor
shows the