MC9S08QG8CDTER Freescale, MC9S08QG8CDTER Datasheet - Page 124

• Manufacturer Part Number: MC9S08QG8CDTER
• Manufacturer: Freescale

Specifications of MC9S08QG8CDTER

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 512Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: TSSOP
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Lead Free Status / RoHS Status: Compliant

Analog-to-Digital Converter (S08ADC10V1)
122
COCO
ADCO
ADCH
Field
AIEN
4:0
7
6
5
Reset:
W
R
Conversion Complete Flag — The COCO flag is a read-only bit which is set each time a conversion is
completed when the compare function is disabled (ACFE = 0). When the compare function is enabled (ACFE =
1) the COCO flag is set upon completion of a conversion only if the compare result is true. This bit is cleared
whenever ADCSC1 is written or whenever ADCRL is read.
0 Conversion not completed
1 Conversion completed
Interrupt Enable — AIEN is used to enable conversion complete interrupts. When COCO becomes set while
AIEN is high, an interrupt is asserted.
0 Conversion complete interrupt disabled
1 Conversion complete interrupt enabled
Continuous Conversion Enable — ADCO is used to enable continuous conversions.
0 One conversion following a write to the ADCSC1 when software triggered operation is selected, or one
1 Continuous conversions initiated following a write to ADCSC1 when software triggered operation is selected.
Input Channel Select — The ADCH bits form a 5-bit field which is used to select one of the input channels. The
input channels are detailed in
The successive approximation converter subsystem is turned off when the channel select bits are all set to 1.
This feature allows for explicit disabling of the ADC and isolation of the input channel from all sources.
Terminating continuous conversions this way will prevent an additional, single conversion from being performed.
It is not necessary to set the channel select bits to all 1s to place the ADC in a low-power state when continuous
conversions are not enabled because the module automatically enters a low-power state when a conversion
completes.
conversion following assertion of ADHWT when hardware triggered operation is selected.
Continuous conversions are initiated by an ADHWT event when hardware triggered operation is selected.
COCO
7
0
ADCH
00000
00001
00010
00011
00100
00101
00110
= Unimplemented or Reserved
AIEN
Figure 9-3. Status and Control Register (ADCSC1)
0
6
Table 9-3. ADCSC1 Register Field Descriptions
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Figure 9-4. Input Channel Select
Figure
ADCO
Input Select
0
5
AD0
AD1
AD2
AD3
AD4
AD5
AD6
9-4.
1
4
Description
1
3
ADCH
ADCH
10000
10001
10010
10011
10100
10101
10110
1
2
Freescale Semiconductor
1
1
Input Select
AD16
AD17
AD18
AD19
AD20
AD21
AD22
1
0