MC9S08QG8CDTER Freescale, MC9S08QG8CDTER Datasheet - Page 148

• Manufacturer Part Number: MC9S08QG8CDTER
• Manufacturer: Freescale

Specifications of MC9S08QG8CDTER

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 512Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: TSSOP
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Lead Free Status / RoHS Status: Compliant

Internal Clock Source (S08ICSV1)
10.1.4.5
In FLL bypassed external mode, the FLL is enabled and controlled by an external reference clock, but is
bypassed. The ICS supplies a clock derived from the external reference clock. The external reference clock
can be an external crystal/resonator supplied by an OSC controlled by the ICS, or it can be another external
clock source. The BDC clock is supplied from the FLL.
10.1.4.6
In FLL bypassed external low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock
derived from the external reference clock. The external reference clock can be an external crystal/resonator
supplied by an OSC controlled by the ICS, or it can be another external clock source. The BDC clock is
not available.
10.1.4.7
In stop mode, the FLL is disabled and the internal or external reference clock can be selected to be enabled
or disabled. The BDC clock is not available. ICS does not provide an MCU clock source.
10.1.5
This section contains the ICS block diagram.
146
Block Diagram
RANGE
FLL Bypassed Externa
FLL Bypassed Externa
Stop (STOP)
HGO
IREFS
Figure 10-2. Internal Clock Source (ICS) Block Diagram
External Reference
Clock Source
n=0-7
RDIV
/ 2
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Optional
Block
n
IREFSTEN
Reference
Internal
RDIV_CLK
TRIM
Clock
9
l (FBE)
l Low Power (FBELP)
EREFSTEN
EREFS
Filter
DCO
LP
FLL
ERCLKEN
IRCLKEN
9
Internal Clock Source Block
CLKS
DCOOUT
n=0-3
BDIV
/ 2
/ 2
n
ICSERCLK
ICSIRCLK
ICSOUT
ICSLCLK
ICSFFCLK
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